ispGAL22V10 Device Datasheet June 2010 All Devices Discontinued Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN ispGAL22V10C-7LJ PCN 06-07 ispGAL22V10C-7LJN ispGAL22V10C-10LJ ispGAL22V10C-10LJN ispGAL22V10C-15LJ ispGAL22V10C ispGAL22V10C-15LJN Discontinued ispGAL22V10C-15LJI PCN 09-10 ispGAL22V10C-7LK ispGAL22V10C-10LK ispGAL22V10C-15LK ispGAL22V10C-15LKI 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: ispGAL22V10 2 In-System Programmable E CMOS PLD Generic Array Logic Features Functional Block Diagram IN-SYSTEM PROGRAMMABLE (5-V ONLY) RESET I/CLK 4-Wire Serial Programming Interface 8 Minimum 10,000 Program/Erase Cycles OLMC I/O/Q Built-in Pull-Down on SDI Pin Eliminates Discrete I Resistor on Board (ispGAL22V10C Only) 10 OLMC 2 I/O/Q I HIGH PERFORMANCE E CMOS TECHNOLOGY 7.5 ns Maximum Propagation Delay 12 Fmax = 111 MHz I OLMC I/O/Q 5 ns Maximum from Clock Input to Data Output UltraMOS Advanced CMOS Technology 14 I OLMC I/O/Q ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS COMPATIBLE WITH STANDARD 22V10 DEVICES I 16 Fully Function/Fuse-Map/Parametric Compatible OLMC I/O/Q with Bipolar and CMOS 22V10 Devices I 2 16 E CELL TECHNOLOGY OLMC I/O/Q In-System Programmable Logic I 100% Tested/100% Yields 14 High Speed Electrical Erasure (<100ms) OLMC I/O/Q I 20 Year Data Retention 12 TEN OUTPUT LOGIC MACROCELLS OLMC I I/O/Q Maximum Flexibility for Complex Logic Designs APPLICATIONS INCLUDE: 10 I DMA Control OLMC I/O/Q State Machine Control I High Speed Graphics Processing 8 OLMC I/O/Q SDO Software-Driven Hardware Configuration SDI PROGRAMMING LOGIC MODE ELECTRONIC SIGNATURE FOR IDENTIFICATION PRESET SCLK LEAD-FREE PACKAGE OPTIONS Description Pin Configuration The ispGAL22V10, at 7.5ns maximum propagation delay time, PLCC combines a high performance CMOS process with Electrically Eras- SSOP 2 able (E ) floating gate technology to provide the industry s first in- 2 system programmable 22V10 device. E technology offers high speed (<100ms) erase times, providing the ability to reprogram or 4 228 26 reconfigure the device quickly and efficiently. SCLK 1 28 Vcc I 5 25 I/O/Q I/CLK I/O/Q The generic architecture provides maximum design flexibility by al- I I/O/Q I I/O/Q I I/O/Q lowing the Output Logic Macrocell (OLMC) to be configured by the I I/O/Q 23 ispGAL I 7 I/O/Q user. The ispGAL22V10 is fully function/fuse map/parametric com- ispGAL22V10 I I/O/Q 7 22 SDO I 22V10 MODE SDO patible with standard bipolar and CMOS 22V10 devices. The stan- MODE I/O/Q Top View I I/O/Q dard PLCC package provides the same functional pinout as the Top View I 9 21 I/O/Q I I/O/Q standard 22V10 PLCC package with No-Connect pins being used I I/O/Q I I/O/Q I I/O/Q for the ISP interface signals. I I I 11 19 I/O/Q 12 14 16 18 GND 14 15 SDI Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lat- tice Semiconductor delivers 100% field programmability and func- tionality of all GAL products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. Copyright 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556