ispLSI 1016E In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC 2000 PLD Gates 32 I/O Pins, Four Dedicated Inputs 96 Registers A0 B7 High-Speed Global Interconnect DQ A1 B6 Wide Input Gating for Fast Counters, State A2 DQ B5 Machines, Address Decoders, etc. Logic GLB B4 A3 Array DQ Small Logic Block Size for Random Logic A4 B3 DQ 2 HIGH-PERFORMANCE E CMOS TECHNOLOGY A5 B2 fmax = 125 MHz Maximum Operating Frequency A6 B1 tpd = 7.5 ns Propagation Delay Global Routing Pool (GRP) A7 B0 TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable CLK Non-Volatile 100% Tested at Time of Manufacture 0139C1-isp Unused Product Term Shutdown Saves Power Description IN-SYSTEM PROGRAMMABLE The ispLSI 1016E is a High Density Programmable Logic In-System Programmable (ISP) 5V Only Device containing 96 Registers, 32 Universal I/O pins, Increased Manufacturing Yields, Reduced Time-to- four Dedicated Input pins, three Dedicated Clock Input Market and Improved Product Quality pins, one Global OE input pin and a Global Routing Pool Reprogram Soldered Device for Faster Prototyping (GRP). The GRP provides complete interconnectivity OFFERS THE EASE OF USE AND FAST SYSTEM between all of these elements. The ispLSI 1016E offers SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY 5V non-volatile in-system programmability of the logic, as OF FIELD PROGRAMMABLE GATE ARRAYS well as the interconnect to provide truly reconfigurable Complete Programmable Device Can Combine Glue systems. A functional superset of the ispLSI 1016 Logic and Structured Designs architecture, the ispLSI 1016E device adds a new global Enhanced Pin Locking Capability output enable pin. Three Dedicated Clock Input Pins The basic unit of logic on the ispLSI 1016E device is the Synchronous and Asynchronous Clocks Generic Logic Block (GLB). The GLBs are labeled A0, Programmable Output Slew Rate Control to A1...B7 (see Figure 1). There are a total of 16 GLBs in the Minimize Switching Noise ispLSI 1016E device. Each GLB has 18 inputs, a Flexible Pin Placement programmable AND/OR/Exclusive OR array, and four Optimized Global Routing Pool Provides Global outputs which can be configured to be either combinatorial Interconnectivity or registered. Inputs to the GLB come from the GRP and Lead-Free Package Options dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Specifications ispLSI 1016E Functional Block Diagram Figure 1. ispLSI 1016E Functional Block Diagram Generic Logic Blocks (GLBs) GOE 0/IN 3 MODE/IN 2 I/O 31 B7 I/O 30 I/O 0 I/O 29 A0 I/O 1 B6 I/O 28 I/O 2 I/O 3 A1 I/O 27 B5 I/O 26 I/O 4 I/O 25 A2 I/O 5 B4 I/O 24 Global I/O 6 Routing A3 I/O 7 I/O 23 Pool B3 I/O 22 (GRP) I/O 8 A4 I/O 21 B2 I/O 9 I/O 20 I/O 10 A5 I/O 11 B1 I/O 19 I/O 18 I/O 12 A6 I/O 17 B0 I/O 13 I/O 16 I/O 14 A7 I/O 15 SDI/IN 0 CLK 0 SDO/IN 1 CLK 1 Clock CLK 2 Distribution IOCLK 0 Network IOCLK 1 Megablock ispEN 0139B(1a)-isp *Note: Y1 and RESET are multiplexed on the same pin The GRP has, as its inputs, the outputs from all of the The device also has 32 I/O cells, each of which is directly GLBs and all of the inputs from the bi-directional I/O cells. connected to an I/O pin. Each I/O cell can be individually All of these signals are made available to the inputs of the programmed to be a combinatorial input, registered in- GLBs. Delays through the GRP have been equalized to put, latched input, output or bi-directional minimize timing skew. I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source Clocks in the ispLSI 1016E device are selected using the 4 mA or sink 8 mA. Each output can be programmed Clock Distribution Network. Three dedicated clock pins independently for fast or slow output slew rate to mini- (Y0, Y1 and Y2) are brought into the distribution network, mize overall output switching noise. and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs Eight GLBs, 16 I/O cells, two dedicated inputs and one and I/O cells. The Clock Distribution Network can also be ORP are connected together to make a Megablock (see driven from a special clock GLB (B0 on the ispLSI 1016E Figure 1). The outputs of the eight GLBs are connected device). The logic of this GLB allows the user to create an to a set of 16 universal I/O cells by the ORP. Each ispLSI internal clock from a combination of internal signals 1016E device contains two Megablocks. within the device. 2 USE ispLSI 1016EA FOR NEW DESIGNS Input Bus Output Routing Pool (ORP) Y0 Y1/RESET* SCLK/Y2 Output Routing Pool (ORP) lnput Bus