Select devices have been discontinued. See Ordering Information section for product status. ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram ENHANCEMENTS Output Routing Pool (ORP) Output Routing Pool (ORP) ispLSI 2128A is Fully Form and Function Compatible D7 D6 D5 D4 D3 D2 D1 D0 to the ispLSI 2128, with Identical Timing Specifcations and Packaging A0 C7 ispLSI 2128A is Built on an Advanced 0.35 Micron 2 A1 C6 E CMOS Technology HIGH DENSITY PROGRAMMABLE LOGIC DQ A2 C5 6000 PLD Gates A3 C4 DQ 128 I/O Pins, Eight Dedicated Inputs Logic 128 Registers A4 C3 GLB Array DQ High Speed Global Interconnect Wide Input Gating for Fast Counters, State A5 C2 DQ Machines, Address Decoders, etc. A6 C1 Small Logic Block Size for Random Logic 2 HIGH PERFORMANCE E CMOS TECHNOLOGY A7 C0 Global Routing Pool (GRP) fmax = 100 MHz Maximum Operating Frequency B0 B1 B2 B3 B4 B5 B6 B7 tpd = 10 ns Propagation Delay Output Routing Pool (ORP) Output Routing Pool (ORP) TTL Compatible Inputs and Outputs 0139(9A)/2128 Electrically Erasable and Reprogrammable Non-Volatile Description 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power The ispLSI 2128 and 2128A are High Density Program- IN-SYSTEM PROGRAMMABLE mable Logic Devices. The devices contains128 Registers, In-System Programmable (ISP) 5V Only 128 Universal I/O pins, eight Dedicated Input pins, three Increased Manufacturing Yields, Reduced Time-to- Dedicated Clock Input pins, two dedicated Global OE Market and Improved Product Quality input pins and a Global Routing Pool (GRP). The GRP Reprogram Soldered Devices for Faster Prototyping provides complete interconnectivity between all of these OFFERS THE EASE OF USE AND FAST SYSTEM elements. The ispLSI 2128 and 2128A feature 5V in- SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY system programmability and in-system diagnostic OF FIELD PROGRAMMABLE GATE ARRAYS capabilities. The ispLSI 2128 and 2128A offer non- Complete Programmable Device Can Combine Glue volatile reprogrammability of the logic, as well as the Logic and Structured Designs interconnect to provide truly reconfigurable systems. Enhanced Pin Locking Capability The basic unit of logic on these devices is the Generic Three Dedicated Clock Input Pins Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 Synchronous and Asynchronous Clocks (Figure 1). There are a total of 32 GLBs in the ispLSI 2128 Programmable Output Slew Rate Control to and 2128A devices. Each GLB is made up of four Minimize Switching Noise macrocells. Each GLB has 18 inputs, a programmable Flexible Pin Placement AND/OR/Exclusive OR array, and four outputs which can Optimized Global Routing Pool Provides Global Interconnectivity be configured to be either combinatorial or registered. Lead-Free Package Options Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556 Select devices have been discontinued. See Ordering Information section for product status. Specifications ispLSI 2128/A Functional Block Diagram Figure 1. ispLSI 2128/A Functional Block Diagram RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock IN 5 Generic Logic D7 D6 D5 D4 D3 D2 D1 D0 Blocks (GLBs) IN 4 I/O 95 C7 I/O 94 I/O 93 I/O 92 I/O 0 A0 I/O 1 I/O 91 C6 I/O 2 I/O 90 I/O 3 I/O 89 I/O 88 I/O 4 I/O 87 A1 I/O 5 I/O 86 C5 I/O 6 I/O 85 I/O 7 I/O 84 I/O 8 I/O 9 I/O 83 A2 I/O 82 I/O 10 C4 I/O 11 Global I/O 81 I/O 80 I/O 12 Routing I/O 79 I/O 13 A3 I/O 78 I/O 14 Pool C3 I/O 77 I/O 15 I/O 76 (GRP) I/O 16 I/O 75 I/O 17 A4 I/O 74 I/O 18 C2 I/O 73 I/O 19 I/O 72 I/O 20 I/O 71 I/O 21 I/O 70 A5 I/O 22 I/O 69 C1 I/O 23 I/O 68 I/O 24 I/O 67 I/O 25 I/O 66 I/O 26 A6 I/O 65 I/O 27 C0 I/O 64 I/O 28 I/O 29 I/O 30 A7 I/O 31 SCLK/IN 0 B0 B1 B2 B3 B4 B5 B6 B7 MODE/IN 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus ispEN 0139(10A)/2128 The device also has 128 I/O cells, each of which is The GRP has as its inputs, the outputs from all of the directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells. individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the output or bi-directional I/O pin with 3-state control. The GLBs. Delays through the GRP have been equalized to signal levels are TTL compatible voltages and the output minimize timing skew. drivers can source 4 mA or sink 8 mA. Each output can Clocks in the ispLSI 2128 and 2128A devices are se- be programmed independently for fast or slow output lected using the dedicated clock pins. Three dedicated slew rate to minimize overall output switching noise. clock pins (Y0, Y1, Y2) or an asynchronous clock can be Eight GLBs, 32 I/O cells, two dedicated inputs and two selected on a GLB basis. The asynchronous or Product ORPs are connected together to make a Megablock Term clock can be generated in any GLB for its own clock. (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the two ORPs. Each ispLSI 2128 and 2128A device contains four Megablocks. 2 USE ispLSI 2128E FOR NEW DESIGNS Input Bus Output Routing Pool (ORP) Output Routing Pool (ORP) IN 2 IN 3 I/O 32 I/O 33 I/O 34 I/O 127 I/O 35 I/O 126 I/O 36 I/O 125 I/O 37 I/O 124 I/O 38 I/O 39 I/O 123 I/O 122 I/O 40 I/O 121 I/O 41 I/O 120 I/O 42 I/O 119 I/O 43 I/O 118 I/O 44 I/O 117 I/O 45 I/O 116 I/O 46 I/O 115 I/O 47 I/O 114 I/O 48 I/O 113 I/O 49 I/O 112 I/O 50 I/O 111 I/O 51 I/O 110 I/O 52 I/O 109 I/O 53 I/O 108 I/O 54 I/O 107 I/O 55 I/O 106 I/O 56 I/O 105 I/O 57 I/O 104 I/O 58 I/O 103 I/O 59 I/O 102 I/O 60 I/O 101 I/O 61 I/O 100 I/O 62 I/O 99 I/O 63 I/O 98 I/O 97 I/O 96 Y0 CLK 0 SDI/IN 7 Y1 CLK 1 SDO/IN 6 Y2 CLK 2 Output Routing Pool (ORP) Output Routing Pool (ORP) Input Bus