JESD-204B-E3-UT1 Lattice

JESD204B IP Core User Guide FPGA-IPUG-02010 Version 2.3 June 2017 JESD204B IP Core User Guide Contents 1. Introduction .................................................................................................................................................................. 4 1.1. Quick Facts .......................................................................................................................................................... 4 1.2. Features ............................................................................................................................................................... 5 1.3. What is Not Supported ........................................................................................................................................ 5 1.4. Conventions......................................................................................................................................................... 6 1.5. Data Ordering and Data Types ............................................................................................................................ 6 1.6. Signal Names ....................................................................................................................................................... 6 2. Functional Description .................................................................................................................................................. 7 2.1. Rx Core ................................................................................................................................................................ 7 2.2. Tx Core............................................................................................................................................................... 14 3. Parameter Settings ..................................................................................................................................................... 19 3.1. Configuring JESD204B Core in IPexpress ........................................................................................................... 19 3.2. Configuring JESD204B Core in Clarity Designer ................................................................................................. 21 4. IP Core Generation and Evaluation ............................................................................................................................. 22 4.1. Licensing the IP .................................................................................................................................................. 22 4.2. Getting Started .................................................................................................................................................. 22 4.3. Creating IP in Clarity Designer ........................................................................................................................... 23 4.4. Generating IP in IPexpress ................................................................................................................................. 27 4.5. Generated IP Directory Structure and Files ....................................................................................................... 28 4.6. Instantiating the IP Core .................................................................................................................................... 29 4.7. Running Functional Simulation ......................................................................................................................... 30 4.7.1. Running Functional Simulation in ModelSim ............................................................................................... 30 4.7.2. Running Functional Simulation in Active HDL .............................................................................................. 30 4.8. Simulation Strategies ........................................................................................................................................ 31 4.9. Simulation Environment .................................................................................................................................... 31 4.10. Synthesizing and Implementing the IP in a Top-Level Design ........................................................................... 32 4.11. Hardware Evaluation ......................................................................................................................................... 32 4.11.1. Enabling Hardware Evaluation in Diamond .................................................................................................. 32 4.12. Updating/Regenerating the IP........................................................................................................................... 32 4.12.1. Regenerating an IP in Clarity Designer ......................................................................................................... 32 5. Application Support .................................................................................................................................................... 34 References .......................................................................................................................................................................... 35 Technical Support Assistance ............................................................................................................................................. 35 Appendix A. Resource Utilization ....................................................................................................................................... 36 LatticeECP3-70 Utilization .............................................................................................................................................. 36 LFE5UM-85 Utilization .................................................................................................................................................... 36 LFE5UM5G-85 Utilization ................................................................................................................................................ 36 Appendix B. Limitations ...................................................................................................................................................... 37 JESD204B 5G IP Core ....................................................................................................................................................... 37 Revision History .................................................................................................................................................................. 38 2013-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-IPUG-02010-2.3