LA-MachXO Automotive Family Data Sheet DS1003 Version 01.5, November 2007 LA-MachXO Automotive Family Data Sheet Introduction April 2006 Data Sheet DS1003 Programmable sysIO buffer supports wide Features range of interfaces: Non-volatile, Innitely Recongurable LVCMOS 3.3/2.5/1.8/1.5/1.2 Instant-on powers up in microseconds LVTTL Single chip, no external conguration memory PCI required LVDS, Bus-LVDS, LVPECL, RSDS Excellent design security, no bit stream to sysCLOCK PLLs intercept Up to two analog PLLs per device Recongure SRAM based logic in milliseconds Clock multiply, divide, and phase shifting SRAM and non-volatile memory programmable System Level Support through JTAG port IEEE Standard 1149.1 Boundary Scan Supports background programming of Onboard oscillator non-volatile memory Devices operate with 3.3V, 2.5V, 1.8V or 1.2V AEC-Q100 Tested and Qualied power supply Sleep Mode IEEE 1532 compliant in-system programming Allows up to 100x static current reduction TransFR Reconguration (TFR) Introduction In-eld logic update while system operates The LA-MachXO automotive device family is optimized High I/O to Logic Density to meet the requirements of applications traditionally 256 to 2280 LUT4s addressed by CPLDs and low capacity FPGAs: glue 73 to 271 I/Os with extensive package options logic, bus bridging, bus interfacing, power-up control, Density migration supported and control logic. These devices bring together the best Lead free/RoHS compliant packaging features of CPLD and FPGA devices on a single chip in Embedded and Distributed Memory AEC-Q100 tested and qualied versions. Up to 27.6 Kbits sysMEM Embedded Block RAM The devices use look-up tables (LUTs) and embedded Up to 7.5 Kbits distributed RAM block memories traditionally associated with FPGAs for Dedicated FIFO control logic exible and efcient logic implementation. Through non- volatile technology, the devices provide the single-chip, Flexible I/O Buffer Table 1-1. LA-MachXO Automotive Family Selection Guide Device LAMXO256E/CLAMXO640E/CLAMXO1200ELAMXO2280E LUTs 256 640 1200 2280 Dist. RAM (Kbits) 2.0 6.0 6.25 7.5 EBR SRAM (Kbits) 0 0 9.2 27.6 Number of EBR SRAM Blocks (9 Kbits) 0013 V Voltage 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2 1.2 CC Number of PLLs 0012 Max. I/O 78 159 211 271 Packages 100-pin Lead-Free TQFP (14x14 mm) 78 74 73 73 144-pin Lead-Free TQFP (20x20 mm) 113 113 113 256-ball Lead-Free ftBGA (17x17 mm) 159 211 211 324-ball Lead-Free ftBGA (19x19 mm) 271 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1003 Introduction 01.0