LA-LatticeXP2 Family Data Sheet DS1024 Version 1.5, February 2015LA-LatticeXP2 Family Data Sheet Introduction February 2015 Data Sheet DS1024 Flexible I/O Buffer Features sysIO buffer supports: flexiFLASH Architecture LVCMOS 33/25/18/15/12 LVTTL Instant-on SSTL 33/25/18 class I, II Infinitely reconfigurable HSTL15 class I HSTL18 class I, II Single chip PCI FlashBAK technology LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS Serial TAG memory Pre-engineered Source Synchronous Design security Interfaces AEC-Q100 Tested and Qualified DDR / DDR2 interfaces up to 200 MHz Live Update Technology 7:1 LVDS interfaces support display applications TransFR technology XGMII Secure updates with 128 bit AES encryption Density And Package Options Dual-boot with external SPI 5k to 17k LUT4s, 86 to 358 I/Os sysDSP Block csBGA, ftBGA, TQFP and PQFP packages Three to five blocks for high performance Density migration supported Multiply and Accumulate Flexible Device Configuration 12 to 20 18 x 18 multipliers SPI (master and slave) Boot Flash Interface Each block supports one 36 x 36 multiplier or Dual Boot Image supported four 18 x 18 or eight 9 x 9 multipliers Soft Error Detect (SED) macro embedded Embedded and Distributed Memory System Level Support Up to 276 kbits sysMEM EBR IEEE 1149.1 and IEEE 1532 Compliant Up to 35 kbits Distributed RAM On-chip oscillator for initialization & general use sysCLOCK PLLs Devices operate with 1.2 V power supply Up to four analog PLLs per device Clock multiply, divide and phase shifting Table 1-1. LA-LatticeXP2 Family Selection Guide Device LA-XP2-5 LA-XP2-8LA-XP2-17 LUTs (K) 5 8 17 Distributed RAM (kbits) 10 18 35 EBR SRAM (kbits) 166 221 276 EBR SRAM Blocks 9 12 15 sysDSP Blocks 3 4 5 18 x 18 Multipliers 12 16 20 V Voltage 1.2 1.2 1.2 CC GPLL 224 Max Available I/O 172 201 201 Packages and I/O Combinations 132-Ball csBGA (8 x 8 mm) 86 86 144-Pin TQFP (20 x 20 mm) 100 100 208-Pin PQFP (28 x 28 mm) 146 146 146 256-Ball ftBGA (17 x17 mm) 172 201 201 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1024 Introduction 01.4