MachXO2 Family Data Sheet FPGA-DS-02056 Version 3.4, June 2019MachXO2 Family Data Sheet Introduction June 2019 Data Sheet FPGA-DS-02056 Flexible On-Chip Clocking Features Eight primary clocks Flexible Logic Architecture Up to two edge clocks for high-speed I/O Six devices with 256 to 6864 LUT4s and interfaces (top and bottom sides only) 18 to 334 I/O Up to two analog PLLs per device with Ultra Low Power Devices fractional-n frequency synthesis Advanced 65 nm low power process Wide input frequency range (7 MHz to As low as 22 W standby power 400 MHz) Programmable low swing differential I/O Non-volatile, Infinitely Reconfigurable Stand-by mode and other power saving options Instant-on powers up in microseconds Embedded and Distributed Memory Single-chip, secure solution Up to 240 kbits sysMEM Embedded Block 2 Programmable through JTAG, SPI or I C RAM Supports background programming of non-vola- Up to 54 kbits Distributed RAM tile memory Dedicated FIFO control logic Optional dual boot with external SPI memory On-Chip User Flash Memory TransFR Reconfiguration Up to 256 kbits of User Flash Memory In-field logic update while system operates 100,000 write cycles Enhanced System Level Support 2 Accessible through WISHBONE, SPI, I C and 2 On-chip hardened functions: SPI, I C, timer/ JTAG interfaces counter Can be used as soft processor PROM or as On-chip oscillator with 5.5% accuracy Flash memory Unique TraceID for system tracking Pre-Engineered Source Synchronous I/O One Time Programmable (OTP) mode DDR registers in I/O cells Single power supply with extended operating Dedicated gearing logic range 7:1 Gearing for Display I/O IEEE Standard 1149.1 boundary scan Generic DDR, DDRX2, DDRX4 IEEE 1532 compliant in-system programming Dedicated DDR/DDR2/LPDDR memory with Broad Range of Package Options DQS support TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, High Performance, Flexible I/O Buffer fpBGA, QFN package options Programmable sysI/O buffer supports wide Small footprint package options range of interfaces: As small as 2.5 mm x 2.5 mm LVCMOS 3.3/2.5/1.8/1.5/1.2 Density migration supported LVTTL Advanced halogen-free packaging PCI LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL SSTL 25/18 HSTL 18 MIPI D-PHY Emulated Schmitt trigger inputs, up to 0.5 V hysteresis I/O support hot socketing On-chip differential termination Programmable pull-up or pull-down mode 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 FPGA-DS-02056 Introduction 02.3