LCMXO3L-9400E-5BG256I Lattice

MachXO3 Family Data Sheet FPGA-DS-02032-2.4 February 2019 MachXO3 Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 6 1. Introduction .................................................................................................................................................................. 7 1.1. Features ............................................................................................................................................................... 8 1.1.1. Solutions ......................................................................................................................................................... 8 1.1.2. Flexible Architecture ....................................................................................................................................... 8 1.1.3. Advanced Packaging ....................................................................................................................................... 8 1.1.4. Pre-Engineered Source Synchronous I/O ........................................................................................................ 8 1.1.5. High Performance, Flexible I/O Buffer ............................................................................................................ 8 1.1.6. Flexible On-Chip Clocking ................................................................................................................................ 8 1.1.7. Non-volatile, Multi-time Programmable ......................................................................................................... 8 1.1.8. TransFR Reconfiguration ................................................................................................................................. 8 1.1.9. Enhanced System Level Support ..................................................................................................................... 8 1.1.10. Applications ................................................................................................................................................ 8 1.1.11. Low Cost Migration Path ............................................................................................................................ 8 2. Architecture ................................................................................................................................................................ 10 2.1. Architecture Overview ...................................................................................................................................... 10 2.2. PFU Blocks ......................................................................................................................................................... 12 2.2.1. Slices ............................................................................................................................................................. 12 2.2.2. Modes of Operation ...................................................................................................................................... 14 2.2.3. RAM Mode .................................................................................................................................................... 14 2.2.4. ROM Mode .................................................................................................................................................... 14 2.3. Routing .............................................................................................................................................................. 15 2.4. Clock/Control Distribution Network................................................................................................................... 15 2.4.1. sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................... 17 2.5. sysMEM Embedded Block RAM Memory .......................................................................................................... 20 2.5.1. sysMEM Memory Block ................................................................................................................................ 20 2.5.2. Bus Size Matching ......................................................................................................................................... 20 2.5.3. RAM Initialization and ROM Operation ........................................................................................................ 20 2.5.4. Memory Cascading ....................................................................................................................................... 20 2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes .......................................................................................... 21 2.5.6. FIFO Configuration ........................................................................................................................................ 22 2.5.7. Memory Core Reset ...................................................................................................................................... 22 2.5.8. EBR Asynchronous Reset .............................................................................................................................. 23 2.6. Programmable I/O Cells (PIC) ............................................................................................................................ 24 2.7. PIO ..................................................................................................................................................................... 26 2.7.1. Input Register Block ...................................................................................................................................... 26 2.7.2. Output Register Block ................................................................................................................................... 26 2.7.3. Tri-state Register Block ................................................................................................................................. 27 2.8. Input Gearbox ................................................................................................................................................... 27 2.9. Output Gearbox ................................................................................................................................................. 29 2.10. sysI/O Buffer ...................................................................................................................................................... 31 2.10.1. Typical I/O Behavior during Power-up ..................................................................................................... 31 2.10.2. Supported Standards ................................................................................................................................ 31 2.10.3. sysI/O Buffer Banks ................................................................................................................................... 33 2.11. Hot Socketing .................................................................................................................................................... 34 2.12. On-chip Oscillator .............................................................................................................................................. 34 2.13. Embedded Hardened IP Functions .................................................................................................................... 35 2 2.13.1. Hardened I C IP Core ................................................................................................................................ 35 2.13.2. Hardened SPI IP Core ................................................................................................................................ 36 2.13.3. Hardened Timer/Counter ......................................................................................................................... 38 2.14. User Flash Memory (UFM) ................................................................................................................................ 39 2.15. Standby Mode and Power Saving Options ........................................................................................................ 39 2014-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02032-2.4