LatticeECP2/M Family Data Sheet
DS1006 Version 04.1, September 2013LatticeECP2/M Family Data Sheet
Introduction
July 2012 Data Sheet DS1006
Pre-Engineered Source Synchronous I/O
Features
DDR registers in I/O cells
High Logic Density for System Integration
Dedicated gearing logic
6K to 95K LUTs
Source synchronous standards support
90 to 583 I/Os
SPI4.2, SFI4 (DDR Mode), XGMII
Embedded SERDES (LatticeECP2M Only)
High Speed ADC/DAC devices
Data Rates 250 Mbps to 3.125 Gbps
Dedicated DDR and DDR2 memory support
Up to 16 channels per device
DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
PCI Express, Ethernet (1GbE, SGMII), OBSAI,
Dedicated DQS support
CPRI and Serial RapidIO.
Programmable sysI/O Buffer Supports
sysDSP Block
Wide Range Of Interfaces
3 to 42 blocks for high performance multiply and
LVTTL and LVCMOS 33/25/18/15/12
accumulate
SSTL 3/2/18 I, II
Each block supports
HSTL15 I and HSTL18 I, II
One 36x36, four 18x18 or eight 9x9 multipliers
PCI and Differential HSTL, SSTL
Flexible Memory Resources
LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
55Kbits to 5308Kbits sysMEM Embedded
Flexible Device Configuration
Block RAM (EBR)
1149.1 Boundary Scan compliant
18Kbit block
Dedicated bank for configuration I/Os
Single, pseudo dual and true dual port
SPI boot flash interface
Byte Enable Mode support
Dual boot images supported
12K to 202Kbits distributed RAM
TransFR I/O for simple field updates
Single port and pseudo dual port
Soft Error Detect macro embedded
sysCLOCK Analog PLLs and DLLs
Optional Bitstream Encryption
Two GPLLs and up to six SPLLs per device
(LatticeECP2/M S Versions Only)
Clock multiply, divide, phase & delay adjust
System Level Support
Dynamic PLL adjustment
ispTRACY internal logic analyzer capability
Two general purpose DLLs per device
On-chip oscillator for initialization & general use
1.2V power supply
Table 1-1. LatticeECP2 (Including S-Series) Family Selection
Device ECP2-6ECP2-12ECP2-20ECP2-35ECP2-50ECP2-70
LUTs (K) 6 12 21 32 48 68
Distributed RAM (Kbits) 1224426496 136
EBR SRAM (Kbits) 55 221 276 332 387 1032
EBR SRAM Blocks 3 12 15 18 21 60
sysDSP Blocks 3 6 7 8 18 22
18x18 Multipliers 1224283272 88
GPLL + SPLL + DLL 2+0+2 2+0+2 2+0+2 2+0+2 2+2+2 2+4+2
Maximum Available I/O 190 297 402 450 500 583
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm) 90 93
208-pin PQFP (28 x 28 mm) 131 131
256-ball fpBGA (17 x 17 mm) 190 193 193
484-ball fpBGA (23 x 23 mm) 297 331 331 339
672-ball fpBGA (27 x 27 mm) 402 450 500 500
900-ball fpBGA (31 x 31 mm) 583
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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