LatticeECP3 Family Data Sheet Preliminary DS1021 Version 01.6, March 2010LatticeECP3 Family Data Sheet Introduction November 2009 Preliminary Data Sheet DS1021 Dedicated read/write levelling functionality Features Dedicated gearing logic Higher Logic Density for Increased System Source synchronous standards support Integration ADC/DAC, 7:1 LVDS, XGMII 17K to 149K LUTs High Speed ADC/DAC devices 133 to 586 I/Os Dedicated DDR/DDR2/DDR3 memory with DQS Embedded SERDES support 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit Optional Inter-Symbol Interference (ISI) SERDES, and 8-bit SERDES modes correction on outputs Data Rates 230 Mbps to 3.2 Gbps per channel Programmable sysI/O Buffer Supports for all other protocols Wide Range of Interfaces Up to 16 channels per device: PCI Express, On-chip termination SONET/SDH, Ethernet (1GbE, SGMII, XAUI), Optional equalization filter on inputs CPRI, SMPTE 3G and Serial RapidIO LVTTL and LVCMOS 33/25/18/15/12 sysDSP SSTL 33/25/18/15 I, II Fully cascadable slice architecture HSTL15 I and HSTL18 I, II 12 to 160 slices for high performance multiply PCI and Differential HSTL, SSTL and accumulate LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS Powerful 54-bit ALU operations Flexible Device Configuration Time Division Multiplexing MAC Sharing Dedicated bank for configuration I/Os Rounding and truncation SPI boot flash interface Each slice supports Dual-boot images supported Half 36x36, two 18x18 or four 9x9 multipliers Slave SPI Advanced 18x36 MAC and 18x18 Multiply- TransFR I/O for simple field updates Multiply-Accumulate (MMAC) operations Soft Error Detect embedded macro Flexible Memory Resources System Level Support Up to 6.85Mbits sysMEM Embedded Block IEEE 1149.1 and IEEE 1532 compliant RAM (EBR) Reveal Logic Analyzer 36K to 303K bits distributed RAM ORCAstra FPGA configuration utility sysCLOCK Analog PLLs and DLLs On-chip oscillator for initialization & general use Two DLLs and up to ten PLLs per device 1.2V core power supply Pre-Engineered Source Synchronous I/O DDR registers in I/O cells Table 1-1. LatticeECP3 Family Selection Guide Device ECP3-17ECP3-35ECP3-70ECP3-95ECP3-150 LUTs (K) 17336792 149 sysMEM Blocks (18Kbits) 38 72 240 240 372 Embedded Memory (Kbits) 700 1327 4420 4420 6850 Distributed RAM Bits (Kbits) 36 68 145 188 303 18X18 Multipliers 24 64 128 128 320 SERDES (Quad) 11334 PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2 Packages and SERDES Channels/ I/O Combinations 256 ftBGA (17x17 mm) 4 / 133 4 / 133 484 fpBGA (23x23 mm) 4 / 222 4 / 295 4 / 295 4 / 295 672 fpBGA (27x27 mm) 4 / 310 8 / 380 8 / 380 8 / 380 1156 fpBGA (35x35 mm) 12 / 490 12 / 490 16 / 586 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1021 Introduction 01.3