LFE5UM-85F-7BG756I Lattice

ECP5 and ECP5-5G Family Data Sheet FPGA-DS-02012-2.1 April 2019 ECP5 and ECP5-5G Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 8 1. General Description ...................................................................................................................................................... 9 1.1. Features ............................................................................................................................................................... 9 2. Architecture ................................................................................................................................................................ 11 2.1. Overview ........................................................................................................................................................... 11 2.2. PFU Blocks ......................................................................................................................................................... 12 2.2.1. Slice ............................................................................................................................................................... 13 2.2.2. Modes of Operation ...................................................................................................................................... 16 2.2.2.1. Logic Mode ........................................................................................................................................... 16 2.2.2.2. Ripple Mode ......................................................................................................................................... 16 2.2.2.3. RAM Mode ........................................................................................................................................... 16 2.2.2.4. ROM Mode ........................................................................................................................................... 17 2.3. Routing .............................................................................................................................................................. 17 2.4. Clocking Structure ............................................................................................................................................. 17 2.4.1. sysCLOCK PLL................................................................................................................................................. 17 2.5. Clock Distribution Network ............................................................................................................................... 19 2.5.1. Primary Clocks ............................................................................................................................................... 19 2.5.1.1. Dynamic Clock Control ......................................................................................................................... 20 2.5.1.2. Dynamic Clock Select ........................................................................................................................... 20 2.5.2. Edge Clock ..................................................................................................................................................... 20 2.6. Clock Dividers .................................................................................................................................................... 21 2.7. DDRDLL .............................................................................................................................................................. 22 2.8. sysMEM Memory .............................................................................................................................................. 23 2.8.1. sysMEM Memory Block ................................................................................................................................ 23 2.8.2. Bus Size Matching ......................................................................................................................................... 24 2.8.3. RAM Initialization and ROM Operation ........................................................................................................ 24 2.8.4. Memory Cascading ....................................................................................................................................... 24 2.8.5. Single, Dual and Pseudo-Dual Port Modes ................................................................................................... 24 2.8.6. Memory Core Reset ...................................................................................................................................... 25 2.9. sysDSP Slice .................................................................................................................................................... 25 2.9.1. sysDSP Slice Approach Compared to General DSP ....................................................................................... 25 2.9.2. sysDSP Slice Architecture Features ............................................................................................................... 26 2.10. Programmable I/O Cells .................................................................................................................................... 30 2.11. PIO ..................................................................................................................................................................... 32 2.11.1. Input Register Block .................................................................................................................................. 32 2.11.1.1. Input FIFO ............................................................................................................................................. 33 2.11.2. Output Register Block ............................................................................................................................... 33 2.12. Tristate Register Block ....................................................................................................................................... 34 2.13. DDR Memory Support ....................................................................................................................................... 35 2.13.1. DQS Grouping for DDR Memory ............................................................................................................... 35 2.13.2. DLL Calibrated DQS Delay and Control Block (DQSBUF) ........................................................................... 36 2.14. sysI/O Buffer ...................................................................................................................................................... 38 2.14.1. sysI/O Buffer Banks................................................................................................................................... 38 2.14.2. Typical sysI/O I/O Behavior during Power-up ........................................................................................... 39 2.14.3. Supported sysI/O Standards ..................................................................................................................... 39 2.14.4. On-Chip Programmable Termination ....................................................................................................... 40 2.14.5. Hot Socketing............................................................................................................................................ 40 2.15. SERDES and Physical Coding Sublayer ............................................................................................................... 41 2.15.1. SERDES Block ............................................................................................................................................ 43 2.15.2. PCS ............................................................................................................................................................ 43 2.15.3. SERDES Client Interface Bus ..................................................................................................................... 44 2.16. Flexible Dual SERDES Architecture .................................................................................................................... 44 2014-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02012-2.1