LIF-MD6000-6UWG36ITR50 Lattice

CrossLink Family Data Sheet FPGA-DS-02007 Version 1.5 July 2018 CrossLink Family Data Sheet Contents Acronyms in This Document ................................................................................................................................................. 5 1. General Description ...................................................................................................................................................... 6 1.1. Features ............................................................................................................................................................... 6 2. Product Feature Summary ............................................................................................................................................ 7 3. Architecture Overview .................................................................................................................................................. 8 3.1. MIPI D-PHY Blocks ............................................................................................................................................... 9 3.2. Programmable I/O Banks .................................................................................................................................. 14 3.3. sysI/O Buffers .................................................................................................................................................... 15 3.3.1. Programmable PULLMODE Settings ............................................................................................................. 15 3.3.2. Output Drive Strength ................................................................................................................................... 15 3.3.3. On-Chip Termination .................................................................................................................................... 15 3.4. Programmable FPGA Fabric .............................................................................................................................. 16 3.4.1. PFU Blocks ..................................................................................................................................................... 16 3.4.2. Slice ............................................................................................................................................................... 17 3.5. Clocking Structure ............................................................................................................................................. 19 3.5.1. sysCLK PLL ..................................................................................................................................................... 19 3.5.2. Primary Clocks ............................................................................................................................................... 20 3.5.3. Edge Clocks ................................................................................................................................................... 20 3.5.4. Dynamic Clock Enables ................................................................................................................................. 21 3.5.5. Internal Oscillator (OSCI) ............................................................................................................................... 21 3.6. Embedded Block RAM Overview ....................................................................................................................... 22 3.7. Power Management Unit .................................................................................................................................. 23 3.7.1. PMU State Machine ...................................................................................................................................... 23 2 3.8. User I C IP .......................................................................................................................................................... 24 3.9. Programming and Configuration ....................................................................................................................... 25 4. DC and Switching Characteristics ................................................................................................................................ 26 4.1. Absolute Maximum Ratings .............................................................................................................................. 26 4.2. Recommended Operating Conditions ............................................................................................................... 26 4.3. Power Supply Ramp Rates ................................................................................................................................. 27 4.4. Power-On-Reset Voltage Levels ........................................................................................................................ 27 4.5. ESD Performance ............................................................................................................................................... 27 4.6. DC Electrical Characteristics .............................................................................................................................. 28 4.7. CrossLink Supply Current................................................................................................................................... 29 4.8. Power Management Unit (PMU) Timing ........................................................................................................... 30 4.9. sysI/O Recommended Operating Conditions .................................................................................................... 30 4.10. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 31 4.11. sysI/O Differential Electrical Characteristics ..................................................................................................... 31 4.11.1. LVDS/subLVDS/SLVS200 ........................................................................................................................... 31 4.11.2. Hardened MIPI D-PHY I/Os ....................................................................................................................... 32 4.12. CrossLink Maximum General Purpose I/O Buffer Speed ................................................................................... 33 4.13. CrossLink External Switching Characteristics .................................................................................................... 34 4.14. sysCLOCK PLL Timing ......................................................................................................................................... 40 4.15. Hardened MIPI D-PHY Performance.................................................................................................................. 41 4.16. Internal Oscillators (HFOSC, LFOSC) .................................................................................................................. 41 2 4.17. User I C .............................................................................................................................................................. 41 4.18. CrossLink sysCONFIG Port Timing Specifications .............................................................................................. 42 4.19. SRAM Configuration Time from NVCM ............................................................................................................. 42 4.20. Switching Test Conditions ................................................................................................................................. 43 5. Pinout Information ..................................................................................................................................................... 44 5.1. WLCSP36 Pinout ................................................................................................................................................ 44 5.2. ucfBGA64 Pinout ............................................................................................................................................... 45 5.3. ctfBGA80/cktBGA80 Pinout ............................................................................................................................... 47 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-DS-02007-1.5