ADVANCED DESIGN SOFTWARE
Leading-edge design and implementation tools optimized
for Lattice FPGA architectures
Lattice Diamond design software offers leading-edge design and
Key Features and Benefits
implementation tools optimized for cost-sensitive, low-power Lattice
Design Exploration
FPGA architectures. Diamond is the next generation replacement
Explore design alternatives with Implementations & Strategies
for ispLEVER featuring design exploration, ease of use, improved
Run Manager for accelerating exploration and utilizing multi-
design flow, and numerous other enhancements. This combination
core processors
of new and enhanced features allows users to complete designs
Lattice Synthesis Engine (LSE) for additional synthesis
faster, easier and with better results than before.
exploration options.
D ia mo nd so ftw a re i s a vai l ab l e a s a d ow n lo ad from th e L atti ce
website for both Windows and Linux. Once downloaded and
Ease-of-Use Features
installed, it can be used with either a free license or a subsc ription
Advanced next generation user interface
license.
Report view with message filtering features
Extensive cross-probing support
Diamond Software Free License
File list View for managing multiple constraint, preference,
A free license can be downloaded from the Lattice website. This
debug, timing analyzer, and power calculator files
license provides immediate access to many popular Lattice devices
ECO Editor for specific physical netlist-level changes
s uc h as M a c hX O 2 , M a c hX O , P lat f or m M anager 2, and
Platform Designer tool for mixed signal device applications
Lat t iceXP2 at no cost . I t includes Synopsys Synplif y Pro f or
Programmer for improved programming support
Lattice synthesis and Aldec Active-HDL Lattice Edition II mixed
Improved Design Flow
language simulator.*
New Timing Analyzer view allo ws updated timing analysis,
including clock jitter analysis, without re-implementing the
Diamond Software Subscription License
design
A s ubs c r ipt ion lic ens e pr ov ides s uppor t f or all Lat t ic e F P G A s
Simulation Wizard to easily export designs to multiple
including the Lattice ECP3 devices. It also includes Synopsys
simulators
Synplify Pro for Lattice synthesis and Aldec Active-HDL Lattice
Edition II mixed language simulator*.
Additional Software Included with Diamond
LatticeMico system integration for embedded microprocessor
*Aldec Active-HDL Lattice Edition II simulator is only available for Windows. applications
Floating licenses require the additional ALDEC-USBKEY product.
EPIC full-featured physical netlist-level editor
LATTICESEMI.COMLattice Diamond Key Features
Design Exploration
Use Run Manager view for parallel T he HDL Diagram t ool shows a
Projects / Implementations/
processing of multiple implementations graphical display of the design structure
Strategies
to explore design alternatives for the an d pro vi des BKM (Best Know n
Diamond allows more robust projects
best results Methods) rule checks.
and off ers new capabilit ies f or improved
design exploration. Key features include:
HDL Analysis Tools Synthesis Options
Mixing of Verilog, VHDL, EDIF, and
Hierarchy view automatically parses Lat t ice Synt hesis Engine (LSE) and
schematic sources
and displays the design structure Synplify Pro are available for exploring
Implementations allow multiple versions
Displays post-synthesis and post-map t o achieve best result s. LSE supports
of a design within a single project for
TM TM
design resources MachXO2 and MachXO , while
easy design exploration
Provides easy access to source files S y nplif y P r o is applic able f or all devic es .
Strategies allow implementation recipes
for each hierarchy level These two synthesis options support
to be applied to any implementation within
Options for hierarchy control, test bench Verilog and VHDL languages and uses
a project or shared between projects
generation, and symbol generation Sy nopsys Des ign Compiler Const raint s
Manage and choose files for constraints,
format for constraints.
timing analysis, power calculation, and
hardware debug
Ease of Use
GUI for a New Key GUI Elements Speeding Common Functions
Generation of Tools with ECO Editor & Programmer
Common menu and button locations
The Diamond user interface combines for all views ECO Editor provides easy editing of
l e a d i n g e d g e fe atu re s a n d cu sto mi za ti o n Three user interface sections for tools, common netlist changes without using
while of f ering im proved eas e of us e. projects, and output the EPIC full editor
All t ools open in Views int egrat ed int o Start Page open projects, import Programmer allows easy and intuitive
a common user interface. Once the ispLEVER projects, online help, programming of FPGAs
operation for a single tool is learned, this software updates Deployment Tool creates a device
knowledge can be applied to other tools. Report View centralized location for programming file format for the user s
all reports from implementation tools deployment method
Improved Design Flow
Add clock jitter analysis to improve the Tcl console application allows running
Fast, Easy Timing Analysis
robustness of your design scripts independently
Tim ing A naly s is v iew off er s an eas y - t o-
use graphical environment for navigating
Scripting with Tcl Easy Export to Simulators
timing information.
Tcl command dictionaries for projects, The new Simulation Wizard guides
See timing, schematic, and detailed
netlists, HDL code checking, power you through al l the necessa ry steps to
paths for any constraint graphically
calculation, and hardware debug get your design to Aldec or ModelSim
Easy visual cues provide instant design
In addition to the Tcl console in the simulators in the manner you choose.
feedback
Diamond environment, a separate
Rapidly updated analysis when timing
constraints are changed