TM
ispLever
CCOREORE
Multi-Rate Serial Digital Interface Physical Layer IP Core
Users Guide
January 2012
ipug70_01.2Multi-Rate Serial Data Interface Physical Layer
Lattice Semiconductor IP Core Users Guide
Introduction
Serial Digital Interface (SDI) is the most popular raw video link standard used in television broadcast studios and
video production facilities. Field Programmable Gate Arrays (FPGAs) with SDI interface capability can be used for
acquisition, mixing, storage, editing, processing and format conversion applications. Simpler applications use
FPGAs to acquire SDI data from one or more standard definition (SD) or high definition (HD) sources, perform sim-
ple processing and retransmit the video data in SDI format. Such applications require an SDI physical layer (PHY)
interface and some basic processing blocks such as a color space converter and frame buffer. In more complex
applications, the acquired video receives additional processing, such as video format conversion, filtering, scaling,
graphics mixing and picture-in-picture display. FPGA devices can also be used as a bridge between SDI video
sources and backplane protocols such as PCI Express or Ethernet, with or without any additional video processing.
In an FPGA-based SDI solution, the physical interface portion is often the most challenging part of the solution.
This is because the PHY layer includes several device-dependent components such as high speed I/Os
(inputs/outputs), serializer/deserializer (SERDES), clock/data recovery, word alignment and timing signal detection
logic. Video processing, on the other hand, is algorithmic and is usually achieved using proprietary algorithms
developed by in-house teams. The Lattice Multi-Rate SDI PHY Intellectual Property (IP) Core is a complete SDI
PHY interface that connects to the high-speed SDI serial data on one side and the formatted parallel data on the
other side. It enables faster development of applications for processing, storing and bridging SDI video data. It
comprises the high-speed serial I/Os, SERDES, SDI encoder/decoder, word alignment logic, CRC detection and
checking logic and rate detection logic.
The interface standards and source formats for SDI are specified in several documents published by the Society of
Motion Picture and Television Engineers (SMPTE). The SMPTE standards supported by this IP core are the follow-
ing:
Interface: SMPTE 259M-2006 [1] (SD) and SMPTE 292M-1998 [2] (HD)
SD Source Formats: SMPTE 125M [3] and SMPTE 267M [4] (13.5 MHz only)
HD Source Formats: SMPTE 260M [5], SMPTE 274M [6], SMPTE 295M [7] and SMPTE 296M [8]
The IP core can automatically scan and lock on to any of the supported video standards and formats. Receiving
multiple standards is achieved with the help of an external clock generator that provides SD (27 MHz) or HD (148.5
MHz) rate clocks upon request from the IP core.
Features
Support for dynamic multi-rate SD-SDI/HD-SDI (SMPTE 259[1] and SMPTE 292[2]) interfaces
Support for automatic Rx (receive) rate detection and dynamic Tx (transmit) rate selection
Built-in SERDES programming for multi-rate support
Support for multiple SD sour ce formats: SMPTE 125M [3] and SMPTE 267M [4] (13.5 MHz only)
Support for multiple HD source formats: SMPTE 260M [5], SMPTE 274M [6], SMPTE 295M [7] and SMPTE
296M [8]
Word alignment and timing reference sequence (TRS) detection
Field vertical blanking (vblank) and hori zontal blanking (hblank) identification
CRC computation, error ch ecking and insertion for HD
Line number (LN) decoding and encoding for HD
Interface Diagrams
The top-level interface differs largely between configurations where the SERDES is contained inside the IP core
and where it exists outside the IP core. The top-level interface diagram for configurations when SERDES is con-
2