NCO-DDS-SC-UT2 Lattice

Numerically Controlled Oscillator IP Core Users Guide June 2010 IPUG36 02.5Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 8 Chapter 2. Functional Description ...................................................................................................... 10 Principle of NCO ........................................................................................................................................ 10 Lattice NCO Implementation...................................................................................................................... 11 Sum-of-Angles Memory Reduction ............................................................................................................ 12 Improving Quality of Output ....................................................................................................................... 14 Multi-channel NCO..................................................................................................................................... 16 Quadrature Amplitude Modulation (QAM).................................................................................................. 16 Signal Descriptions ............................................................................................................................................. 17 Latency................................................................................................................................................................ 18 Timing Diagrams ................................................................................................................................................. 18 Chapter 3. Parameter Settings ............................................................................................................ 20 Architecture Tab.................................................................................................................................................. 21 Multi-channel Mode.................................................................................................................................... 22 Wave Characteristics ................................................................................................................................. 22 Phase Correction ....................................................................................................................................... 22 QAM Mode................................................................................................................................................. 22 FSK/PSK Tab...................................................................................................................................................... 23 FSK Mode .................................................................................................................................................. 23 PSK Mode.................................................................................................................................................. 23 Implementation Tab ............................................................................................................................................ 24 Memory Type ............................................................................................................................................. 24 DSP Block.................................................................................................................................................. 24 Data Output Ports ...................................................................................................................................... 24 Optional I/O Ports....................................................................................................................................... 25 Pipeline Tab ........................................................................................................................................................ 25 Pipeline Options......................................................................................................................................... 25 Summary Tab...................................................................................................................................................... 26 Chapter 4. IP Core Generation............................................................................................................. 27 Licensing the IP Core.......................................................................................................................................... 27 Getting Started.................................................................................................................................................... 27 IPexpress-Created Files and Top Level Directory Structure............................................................................... 30 Instantiating the Core.......................................................................................................................................... 31 Running Functional Simulation ........................................................................................................................... 31 Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 32 Hardware Evaluation........................................................................................................................................... 32 Enabling Hardware Evaluation in Diamond:............................................................................................... 32 Enabling Hardware Evaluation in ispLEVER:............................................................................................. 33 Updating/Regenerating the IP Core .................................................................................................................... 33 Regenerating an IP Core in Diamond ........................................................................................................ 33 Regenerating an IP Core in ispLEVER ...................................................................................................... 33 Chapter 5. Support Resources ............................................................................................................ 35 Lattice Technical Support.................................................................................................................................... 35 Online Forums............................................................................................................................................ 35 Telephone Support Hotline ........................................................................................................................ 35 E-mail Support ........................................................................................................................................... 35 Local Support............................................................................................................................................. 35 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG36 02.5, June 2010 2 NCO IP Core Users Guide