PCI-ERC4-E3-U1 Lattice

PCI Express 1.1 Root Complex Lite x1, x4 IP Core Users Guide February 2012 IPUG85 01.1Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 5 PHY Layer.................................................................................................................................................... 5 Data Link Layer............................................................................................................................................ 5 Transaction Layer ........................................................................................................................................ 5 Top Level IP Support ................................................................................................................................... 6 Chapter 2. Functional Description ........................................................................................................ 7 Overview ............................................................................................................................................................... 7 Interface Description ........................................................................................................................................... 18 Transmit TLP Interface............................................................................................................................... 18 Transmit TLP Interface Waveforms for x1 ................................................................................................. 23 Receive TLP Interface................................................................................................................................ 24 Message Decode Interface ................................................................................................................................. 26 Interrupt Signaling Messages..................................................................................................................... 26 Error Signaling Messages.......................................................................................................................... 27 Using the Transmit and Receive Interfaces ........................................................................................................ 28 As a Receiver............................................................................................................................................. 28 As a Transmitter......................................................................................................................................... 29 Chapter 3. Parameter Settings ............................................................................................................ 30 General Tab ........................................................................................................................................................ 31 PCI Express Link Configuration ................................................................................................................. 31 Include Master Loopback Data Path.......................................................................................................... 31 Maximum Payload Size.............................................................................................................................. 31 Include ECRC Support............................................................................................................................... 32 Flow Control Tab................................................................................................................................................. 32 Initial Receive Credits ................................................................................................................................ 32 Infinite PH Credits ...................................................................................................................................... 33 Initial PH Credits Available......................................................................................................................... 33 Infinite PD Credits ...................................................................................................................................... 33 Initial PD Credits Available......................................................................................................................... 33 Infinite NPH Credits.................................................................................................................................... 33 Initial NPH Credits Available ...................................................................................................................... 33 Infinite NPD Credits.................................................................................................................................... 33 Initial NPD Credits Available ...................................................................................................................... 33 Infinite CPLH Credits.................................................................................................................................. 33 Initial CPLH Credits Available .................................................................................................................... 33 Infinite CPLD Credits.................................................................................................................................. 33 Initial CPLD Credits Available .................................................................................................................... 33 Update Flow Control Generation Control................................................................................................... 33 Number of P TLPs Between UpdateFC .................................................................................................... 34 Number of PD TLPs Between UpdateFC .................................................................................................. 34 Number of NP TLPs Between UpdateFC .................................................................................................. 34 Number of NPD TLPs Between UpdateFC ............................................................................................... 34 Number of CPL TLPs Between UpdateFC ................................................................................................ 34 Number of CPLD TLPs Between UpdateFC ............................................................................................. 34 Worst Case Number of 125MHz Clock Cycles Between UpdateFC.......................................................... 34 Chapter 4. IP Core Generation and Evaluation .................................................................................. 35 Licensing the IP Core................................................................................................................................. 35 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG85 01.1, February 2012 2 PCI Express 1.1 RC-Lite x1, x4 IP Core Users Guide