RIO-SERI-T42G5-N1 Lattice

TM ispLever CORECORE Serial RapidIO Physical Layer Interface Users Guide October 2005 ipug26_02.0 Serial RapidIO Physical Layer Interface Lattice Semiconductor Users Guide Introduction RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the need for faster bus speeds in an intra-system interconnect for microprocessors, digital signal processors, communications and network processors. It also offers error management and provides a well-dened architecture for recovering from and reporting transmission errors. RapidIO systems contain endpoint and switch processing elements. The RapidIO interconnect architecture is parti- tioned into a layered hierarchy of specications which includes Logical, Common Transport and Physical layers. The Logical layer denes the operations and transactions by which endpoint processing elements communicate with each other. The Common Transport layer denes how the transactions are routed from one endpoint process- ing elements to another through switch processing elements. The Physical layer denes the interface between two devices and the packet transport mechanism, ow control and electrical characteristics. Currently there are two dened Physical layer specication, an 8-bit or 16-bit wide parallel specication and a 1-lane (1x) or 4-lane (4x) serial specication. This users guide explains the information about Lattices Serial RapidIO Physical Layer specication and interface. The Serial RapidIO Physical Layer core comes with the following documentation and les: Data sheet Users guide Lattice evaluation gate level netlist Simulation model for evaluation Core instantiation template Testbench and testbench coding template The following experience is recommended for the user to implement a design using this IP: Familiarity with the Lattice ORCA ORT82G5/ORT42G5 FPSC architecture Familiarity with simulation, synthesis and Lattice ispLEVER design tools Knowledge of the RapidIO Interconnect Specication Part VI: Physical Layer 1x/4x LP-Serial Specication Rev. 1.2, 06/2002 Features Supports high speed 1x mode (up to 2.5 Gbps) 8B/10B encoding and decoding Clock and Data Recovery (CDR) Lane synchronization CRC generation and checking Error detection Packet/control symbol assembly and de-assembly Simple user interface for easy integration into user logic Targets ORT82G5/ORT42G5 FPSC 2