XAUI-E3-U1 Lattice

LatticeECP3 and ECP5 XAUI IP Core User Guide IPUG115 Version 1.0, April 2015Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 4 Chapter 2. Functional Description ........................................................................................................ 6 XAUI IP Core I/O................................................................................................................................................... 9 Functional Description......................................................................................................................................... 10 XGMII and Slip Buffers............................................................................................................................... 14 XAUI-to-XGMII Translation (Receive Interface)......................................................................................... 15 XGMII-to-XAUI Translation (Transmit Interface)........................................................................................ 16 Management Data Input/Output (MDIO) Interface (Optional) .................................................................... 18 Management Frame Structure ................................................................................................................... 19 Register Descriptions .......................................................................................................................................... 20 Input/Output Timing............................................................................................................................................. 22 XGMII Specifications.................................................................................................................................. 22 XAUI Specifications.................................................................................................................................... 24 MDIO Specifications................................................................................................................................... 24 XAUI IP Configuration Dialog Box....................................................................................................................... 25 Parameter Descriptions....................................................................................................................................... 25 Tx Slip Buffer.............................................................................................................................................. 25 Rx Slip Buffer ............................................................................................................................................. 25 MDIO.......................................................................................................................................................... 25 Chapter 3. Parameter Settings ............................................................................................................ 25 Licensing the IP Core.......................................................................................................................................... 26 IPexpress IP Generation Flow ............................................................................................................................ 26 Getting Started........................................................................................................................................... 26 Chapter 4. IP Core Generation............................................................................................................. 26 IPexpress-Created Files and Top Level Directory Structure............................................................................... 28 Instantiating the Core................................................................................................................................. 30 Running Functional Simulation .................................................................................................................. 30 Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 31 Clarity Designer IP Generation Flow................................................................................................................... 32 Getting Started........................................................................................................................................... 32 Configuring and Placing the IP Core.......................................................................................................... 34 Generating the IP Core .............................................................................................................................. 36 Clarity Designer-Created Files and Top Level Directory Structure ..................................................................... 37 Instantiating the Core................................................................................................................................. 38 Running Functional Simulation .................................................................................................................. 39 Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 39 Hardware Evaluation........................................................................................................................................... 40 Enabling Hardware Evaluation in Diamond................................................................................................ 40 Updating/Regenerating the IP Core .................................................................................................................... 40 Regenerating an IP Core in Diamond ........................................................................................................ 40 Regenerating an IP Core using Clarity Designer ....................................................................................... 41 Lattice Technical Support.................................................................................................................................... 42 References.......................................................................................................................................................... 42 LatticeECP3 ............................................................................................................................................... 42 ECP5.......................................................................................................................................................... 42 Revision History .................................................................................................................................................. 42 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG115 1.0, April 2015 2 LatticeECP3 and ECP5 XAUI IP Core User Guide