XGBE-XGXS-O4-N2 Lattice

TM ispLever CORECORE 10Gb Ethernet XGXS IP Core Users Guide April 2004 ipug15_02 Lattice Semiconductor 10Gb Ethernet XGXS IP Core Users Guide Introduction Lattices 10GbE XGXS core provides an ideal solution that meets the need of todays LAN/WAN applications. The 10GbE XGXS core provides a solution for bridging between 10 Gigabit Media Independent Interface (XGMII) and 10 Gigabit Attachment Unit Interface (XAUI) devices. This core allows designers to focus on the application rather than the XGXS core, resulting in faster time to market. Lattices 10GbE XGXS core is a fully synchronous core developed in conjunction with the Lattice ORCA ORT82G5 FPSC to provide a full solution. For more information on these and other Lattice products, refer to the Lattice web site at www.latticesemi.com. This users guide explains the functionality of the 10GbE XGXS core and how it can be implemented to provide a full XGMII-XAUI bridging solution. It also explains how to achieve the maximum level of performance. The 10GbE XGXS core comes with the documentation and the les listed below: Data sheet Lattice gate level netlist RTL simulation model for evaluation Core instantiation template Features Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on the ORCA ORT82G5 0.6-3.7Gbit/s 8b/10b Backplane Interface FPSC, enabling exible10GbE LAN/WAN application solutions. IP targeted to the ORT82G5 programmable array section implements functionality conforming to IEEE 802.3ae, including: 10GbE Media Independent Interface (XGMII). Slip buffers for clock domain transfer to/from the XGMII interface. Complete translation between XGMII and XAUI PCS layers, including 8b/10b encoding and decoding of Idle, Start, Terminate, Error and Sequence code groups and sequences, and randomized Idle generation in the XAUI transmit direction. 64-bit data/8-bit control packet generator/checker on the XGMII side that supports standard compliant CRPAT and CJPAT generation and checking for XAUI interoperability testing. Standard compliant MDIO/MDC interface. Automatic initialization and synchronization of the embedded core. Interface with the high-speed SERDES block embedded in the ORT82G5 that implements a standard XAUI. XAUI functionality supported by the embedded portion of the ORT82G5, including Eight channels of 3.125Gbits/s serializer/deserializer with 8b10b encoding/decoding (four SERDES chan- nels are used in this application). XAUI compliant lane-by-lane synchronization. Lane deskew functionality. Microprocessor interface programmable via the Series 4 system bus. IP provided in encrypted netlist. ModelSim simulation models and test benches available for free evaluation. General Description The 10 Gigabit Ethernet Extended Sublayer (XGXS) Intellectual Property (IP) Core enables the creation of system solutions for 10 Gigabit Ethernet (10GbE) applications as dened by IEEE 802.3ae. This IP Core targets the pro- grammable array section of the ORCA ORT82G5 FPSC and provides a bridging function between 10 Gigabit Media Independent Interface (XGMII) and 10 Gigabit Attachment Unit Interface (XAUI) devices. 2