M21245-15 3G/HD/SD-SDI Multi-rate Reclocker Rev V6 230 mW power consumption (1.2 V operation) Applications Integrated regulators for multi-voltage operation (1.2 V - 3.3 V) 3G/HD/SD-SDI Video Switchers Electrically independent input, output, and core supply rails 3G/HD/SD-SDI Video Routers Output enable/disable and configurable auto or manual bypass mode 3G/HD/SD-SDI Video Distribution Amplifiers Automatic and manual modes for rate indication and selection DVB-ASI Equipment Loss of Lock (LOL), Loss of Signal (LOS) and data rate Indication Two-wire and four-wire serial interface programmability Features Industrial operating temperature range (-40 C to +85 C) SMPTE 259-C, 292, 424M, and DVB ASI Compliant Optional recovered serial clock output Greater than 0.6 UI Input Jitter Tolerance Integrated 50 input termination Input equalization and output de-emphasis for 40 of FR4 trace The M21245 is a serial digital video reclocker with integrated trace equalization and automatic rate detect (ARD) circuitry. It operates at SDI data rates ranging from 270 Mbps to 2970 Mbps and is compliant to SMPTE 424M, SMPTE 292, and SMPTE 259M-C. At 270 Mbps it also supports DVB-ASI. The M21245 has an input jitter tolerance (IJT) of greater than 0.6 unit intervals (UI) and can provide retimed serial outputs with very low output jitter. The reclocker requires a single external 27 MHz crystal, which is used as the reference clock for all four channels. It includes per-lane analog input equalization for up to 40 of FR4 trace and two connectors in addition to output de-emphasis. This device features integrated supply regulators allowing it to be powered from 1.2 V, 1.8 V, 2.5 V, or 3.3 V supply voltages. When operating at 1.2 V, it consumes only 230 mW at 3G-SDI. Furthermore, the power rails for the core, input, and output circuitry are electrically independent and as such may be connected to different voltage rails on the board. This feature allows the M21245 to be DC-coupled to any upstream or downstream device regardless of its input/output voltage level. The device may be configured by setting the internal registers though standard two-wire and four-wire interfaces. The M21245 is offered in a green and RoHS compliant, 6 mm x 6 mm, 40-pin QFN package. M21245 Block Diagram SDI0P IE SDI0N 50 Buffer SDOAP W/ DE SDI1P SDOAN IE SDI1N 4:1 Reclocker Mux SDI2P IE SDI2N 50 Buffer SDOB/SCLKOP W/ DE SDOB/SCLKON SDI3P IE SDI3N 1 M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. Visit www.macom.com for additional data sheets and product information. For further information and support please visit: M21245-15 3G/HD/SD-SDI Multi-rate Reclocker Rev V6 Ordering Information Part Number Package Operating Temperature M21245G-15* 6x6 mm, 40-pin QFN package -40 C to 85 C * The letter G designator after the part number indicates that the device is RoHS compliant. The RoHS compliant devices are backwards compatible with 225 C reflow profiles. Revision History Revision Level Date Description V6 Released December 2015 Updated package drawing, Figure 3-12. Package effective as of July 2014. Added package dimensions, Figure 3-13. H (V5) Released July 2012 Section 4.6.2: Revised four-wire interface description. Table 1-8: Added 2-state input to V and V . G (V4) Released January 2012 IH IL Section 4.9: Advised using a 10 k pull-up to DV when in interrupt mode. DDIO In the previous revision of this device, M21245G-14, the Loss of Lock (LOL) alarm would be erroneously triggered F (V3) Released January 2011 when pathological signals were used. As a workaround, MACOM recommended masking the faulty LOL alarm by setting register 96h bit 6 to 1b. In the latest version, M21245G-15, the faulty algorithm has been corrected. Therefore, the requirement to mask the LOL alarm has been removed from this data sheet. Please note that this change has been made to be fully backwards compatible, so setting register 96h bit 6 to 1b, while unnecessary, will not affect the function or performance of the device. Ordering Information: Updated part number from -14 to 15. Table 1-7: Updated XTAL and reference clock electrical specifications, input Impedance typical from to 400 k to 200 i input amplitude range from 1.6 V-2.0 V to 0.8 V to 1.2 V and max rise/fall times from 1 ns max to 2 ns typical and 6 ns max. Table 1-8: Updated V from 0.75 to 0.80 x DV and I from 24 mA to 3 mA. OH DDIO OL Figure 3-1: Updated the pinout diagram to reflect new pin naming convention. Table 3-1: Updated table to reflect new pin naming convention. Figure 3-6: Updated figure from pull-down to pull-up. Table 5-1: Updated register map table. Added all registers needed to perform EEPROM checksum. Register 0Ah: Added this register to provide programmability to SDOB De-emphasis. Register 0Eh: De-featured xAlarm status mode. Register 0Eh: Modified Interrupt mode xAlarm pulse widths to reflect their true value with respect to a 10K pull up resistor. Register 82h: Updated chip version from 03h to 04h. Figure 4-3: Updated self bias diagram to reflect conditions necessary for self biased mode. Section 4.6.2: Updated to include the detailed timing description for four-wire interface when conducting a write operation followed by a read operation. Table 4-6: Updated the EEPROM Addresses. Table 4-7: Updated the EEPROM Addresses. Section 4.7.1: Clock Recovery: Updated the data to clock delay to 60 ps. Section 4.2: Included conditions necessary for self biased mode. Section 4.6.1: Added note defeaturing xAlaram pin in hardware control mode. Section 4.9: De-featured xAlarm pin in hardware mode and limited xAlarm pin usage to Interrupt Mode only. 2 M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. Visit www.macom.com for additional data sheets and product information. For further information and support please visit: