XR16M780IB25-F MaxLinear

XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO SEPTEMBER 2008 REV. 1.0.0 FEATURES GENERAL DESCRIPTION Pin-to-pin compatible with XR16L580 in 32-QFN 1 The XR16M780 (M780) is an enhanced Universal and 48-TQFP packages Asynchronous Receiver and Transmitter (UART) with 64 bytes of transmit and receive FIFOs, Intel or Motorola Bus Interface select programmable transmit and receive FIFO trigger 16Mbps maximum data rate levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 3.3V, 12.5 Mbps at Programmable TX/RX FIFO Trigger Levels 2.5V and 7.5 Mbps at 1.8V with 4X data sampling TX/RX FIFO Level Counters rate. Independent TX/RX Baud Rate Generator The Auto RS-485 Half-Duplex Direction control feature simplifies both the hardware and software for Fractional Baud Rate Generator half-duplex RS-485 applications. In addition, the Auto RTS/CTS Hardware Flow Control Multidrop mode with Auto Address detection increases the performance by simplifying the Auto XON/XOFF Software Flow Control software routines. Auto RS-485 Half-Duplex Direction Control The Independent TX/RX Baud Rate Generator Multidrop mode w/ Auto Address Detect feature allows the transmitter and receiver to operate at different baud rates. Power consumption of the Sleep Mode with Automatic Wake-up M780 can be minimized by enabling the sleep mode PowerSave mode and PowerSave mode. Infrared (IrDA 1.0 and 1.1) mode The M780 has a 16550 compatible register set that provide users with operating status and control, 1.62V to 3.63V supply operation receiver error indications, and modem serial interface Crystal oscillator or external clock input controls. An internal loopback capability allows onboard diagnostics. The M780 is available in 32-pin APPLICATIONS QFN, 48-pin TQFP and 25-pin BGA packages. All Personal Digital Assistants (PDA) three packages offer both the 16 mode (Intel bus) interface and the 68 mode (Motorola bus) interface Cellular Phones/Data Devices which allows easy integration with Motorola Battery-Operated Devices processors. Global Positioning System (GPS) NOTE: 1 Covered by U.S. Patent 5,649,122. Bluetooth FIGURE 1. XR16M780 BLOCK DIAGRAM VCC PwrSave (1.62 to 3.63 V) A2:A0 GND D7:D0 UART IOR TX, RX, IOW (R/W ) 64 Byte TX FIFO UART RTS , CTS , CS DTR , DSR , Regs TX & IR RI , CD ENDEC INT (IRQ ) RX Intel or Motorola RESET BRG 64 Byte RX FIFO Data Bus (RESET ) Interface 16/68 XTAL1 Crystal Osc/Buffer XTAL2 Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO REV. 1.0.0 FIGURE 2. PIN OUT ASSIGNMENT FOR 32-PIN QFN AND 48-PIN TQFP PACKAGES IN 16 AND 68 MODE 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 NC DSR 25 16 DSR 25 16 NC CD 26 15 NC CD 26 15 NC RI 14 RI VCC 27 IOR 14 IOR 27 32-pin QFN in VCC 32- pin QFN in 13 28 VCC 13 GND 28 GND Motorola Bus Intel Bus Mode D0 29 29 12 IOW D0 12 R/W Mode 30 D1 XTAL 2 30 XTAL 2 11 D1 11 31 D2 XTAL 1 31 10 D2 10 XTAL 1 32 D3 9 PwrSave D3 32 9 PwrSave 23 4 5 6 78 1 23 4 5 6 78 1 GND VCC 36 35 34 33 32 31 30 29 28 27 26 25 36 35 34 33 32 31 30 29 28 27 26 25 24 37 NC 37 NC 24 NC NC 23 38 CTS 38 NC CTS 23 NC 22 39 39 NC 22 NC DSR DSR 21 40 CD 40 NC CD 21 NC 20 41 41 20 RI NC RI NC 48-TQFP in 48-TQFP in 19 42 42 19 VCC IOR VCC IOR 18 43 43 18 D0 Intel Bus Mode GND D0 Motorola Bus Mode GND 17 44 VCC 44 17 D1 NC D1 NC 16 45 45 16 D2 IOW D2 R/W 15 46 46 15 XTAL2 D3 XTAL2 D3 14 47 47 14 XTAL1 D4 XTAL1 D4 48 13 48 PwrSave 13 NC NC PwrSave 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 GND VCC 2 16/68 NC D5 RESET D6 NC D4 CTS D7 DTR 16/68 RESET NC RTS NC NC D5 DTR INT RX D6 RTS NC TX D7 INT A0 NC RX A1 A0 NC A2 CS TX A1 NC NC CS A2 D4 CTS NC 16/68 16/68 RESET D5 RESET D5 DTR D6 NC D6 RTS D7 DTR D7 IRQ NC RTS NC NC RX A0 IRQ RX TX A1 NC TX CS A2 A0 NC A1 NC A2 CS NC NC