XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS APRIL 2011 REV. 1.0.0 FEATURES GENERAL DESCRIPTION Integrated Level Shifters on CPU interface, UART 1 The XR16M890 (M890) is a single-channel and GPIO signals Universal Asynchronous Receiver and Transmitter (UART) with integrated level shifters and 128 bytes of Intel/Motorola/VLIO Bus Interface select transmit and receive FIFOs. 0 ns address setup/hold times For flexibility in a mixed voltage environment, the 24 Mbps maximum UART data rate M890 has 4 VCC pins. There is a VCC pin for the Up to 16 GPIOs core, a VCC pin for the UART signals, a VCC pin for the CPU interface signals and a VCC pin for the 128-Bytes TX and RX FIFOs GPIO signals. The VCC pins for the UART, GPIO Programmable TX/RX trigger levels and CPU interface signals allow for the M890 to interface with devices operating at different voltage TX/RX FIFO Level Counters levels eliminating the need for external voltage level Independent TX/RX Baud Rate Generator shifters. Fractional Baud Rate Generator The Auto RS-485 Half-Duplex Direction control feature simplifies both the hardware and software for Auto RTS/CTS Hardware Flow Control half-duplex RS-485 applications. In addition, the Auto XON/XOFF Software Flow Control Multidrop mode with Auto Address detection and Address Byte Control features increase the Auto RS-485 Half-Duplex Direction Control performance by simplifying the software routines. Multidrop mode w/ Auto Address Detect (RX) The Independent TX/RX Baud Rate Generator Multidrop mode w/ Address Byte Control (TX) feature allows the transmitter and receiver to operate at different baud rates. In addition, the Fractional Sleep Mode with Automatic Wake-up Baud Rate Generator feature provides flexibility for Infrared (IrDA 1.0 and 1.1) mode crystal/clock frequencies for generating standard and non-standard baud rates. 1.62V to 3.63V supply operation The M890 has programmable transmit and receive 5V tolerant inputs FIFO trigger levels, automatic hardware and software Crystal oscillator or external clock input flow control, and data rates of up to 24 Mbps. Power consumption of the M890 can be minimized by APPLICATIONS enabling the sleep mode. Personal Digital Assistants (PDA) The M890 has a 16550 compatible register set that provide users with operating status and control, Cellular Phones/Data Devices receiver error indications, and modem serial interface Battery-Operated Devices controls. An internal loopback capability allows onboard diagnostics. The M890 has a selectable Global Positioning System (GPS) Intel/Motorola/VLIO bus interface. Bluetooth NOTE: 1 Covered by U.S. Patent 5,649,122. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS REV. 1.0.0 FIGURE 1. XR16M890 BLOCK DIAGRAM VCC BUS VCC CORE VCC UART A2:A0 128-Byte D7:D0 TX TX TX FIFO (AD7:AD0) UART 1.62V- Regs 128-Byte 3.63V RX RX CS RX FIFO I/O LLA Intel/ 1.62V- Buffers RTS IOR Motorola/ Flow Control 3.63V CTS IOW (R/W ) VLIO I/O INT (IRQ ) GPIO 3:0 Bus Buffers RESET Interface (RESET ) VCC GPIO Fractional 16/68 GPIOs BRG VLIO EN 1.62V- EN485 3.63V GPIO 15:4 ENIR I/O Buffers XTAL1 Crystal Oscillator/ XTAL2 Buffer SLEEP/PWRDN ORDERING INFORMATION NUMBER OF OPERATING TEMPERATURE PART NUMBER PACKAGE DEVICE STATUS GPIOS RANGE XR16M890IL32-F QFN-32 4 -40C to +85C Active XR16M890IL32TR-F QFN-32 4 -40C to +85C Active XR16M890IL40-F QFN-40 8 -40C to +85C Active XR16M890IL40TR-F QFN-40 8 -40C to +85C Active XR16M890IM48-F TQFP-48 16 -40C to +85C Active XR16M890IM48TR-F TQFP-48 16 -40C to +85C Active NOTE: TR = Tape and Reel, F = Green / RoHS 2