XR20M1280 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS MAY 2011 REV. 1.0.0 FEATURES GENERAL DESCRIPTION Integrated Level Shifters on CPU interface, UART 1 2 The XR20M1280 (M1280) is a single-channel I C/ and GPIO signals SPI Universal Asynchronous Receiver and 2 Transmitter (UART) with integrated level shifters and Selectable I C/SPI bus interface 128 bytes of transmit and receive FIFOs. 26MHz maximum SPI clock For flexibility in a mixed voltage environment, the 24Mbps maximum UART data rate M1280 has 4 VCC pins. There is a VCC pin for the core, a VCC pin for the UART signals, a VCC pin for Up to 16 GPIOs the CPU interface signals and a VCC pin for the 128-Bytes TX and RX FIFOs GPIO signals. The VCC pins for the UART, GPIO 2 Programmable TX/RX trigger levels and I C/SPI interface signals allow for the M1280 to interface with devices operating at different voltage TX/RX FIFO Level Counters levels eliminating the need for external voltage level Independent TX/RX Baud Rate Generator shifters. The VCC pin for the core voltage helps lower the overall power consumption of applications Fractional Baud Rate Generator that use slower data rates. Auto RTS/CTS Hardware Flow Control The Auto RS-485 Half-Duplex Direction control Auto XON/XOFF Software Flow Control feature simplifies both the hardware and software for half-duplex RS-485 applications. In addition, the Auto RS-485 Half-Duplex Direction Control Multidrop mode with Auto Address detection and Multidrop mode w/ Auto Address Detect (RX) Address Byte Control features increase the performance by simplifying the software routines. Multidrop mode w/ Address Byte Control (TX) The Independent TX/RX Baud Rate Generator Sleep Mode with Automatic Wake-up feature allows the transmitter and receiver to operate Infrared (IrDA 1.0 and 1.1) mode at different baud rates. In addition, the Fractional Baud Rate Generator feature provides flexibility for 1.62V to 3.63V supply operation crystal/clock frequencies for generating standard and 5V tolerant inputs non-standard baud rates. Crystal oscillator or external clock input The M1280 has programmable transmit and receive FIFO trigger levels, automatic hardware and software APPLICATIONS flow control, and data rates of up to 24 Mbps. Power consumption of the M1280 can be minimized by Personal Digital Assistants (PDA) enabling the sleep mode. Cellular Phones/Data Devices The M1280 has a 16550 compatible register set that Battery-Operated Devices provide users with operating status and control, receiver error indications, and modem serial interface Global Positioning System (GPS) controls. An internal loopback capability allows Bluetooth onboard diagnostics. The M1280 has a selectable 2 I C/SPI bus interface. NOTE: 1 Covered by U.S. Patent 5,649,122. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XR20M1280 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS REV. 1.0.0 FIGURE 1. XR20M1280 BLOCK DIAGRAM VCC BUS VCC CORE VCC UART 128-Byte TX TX TX FIFO SCK UART SDA 1.62V- Regs 128-Byte 3.63V A0/CS RX RX RX FIFO I/O A1/SI 2 1.62V- I C/ Buffers SO RTS Flow Control 3.63V SPI CTS IRQ I/O Bus GPIO 3:0 RESET Buffers Interface I2C/SPI VCC GPIO EN485 Fractional GPIOs ENIR BRG 1.62V- 3.63V GPIO 15:4 I/O Buffers XTAL1 Crystal Oscillator/ XTAL2 Buffer SLEEP/PWRDN ORDERING INFORMATION NUMBER OF OPERATING TEMPERATURE PART NUMBER PACKAGE DEVICE STATUS GPIOS RANGE XR20M1280IL24-F QFN-24 4 -40C to +85C Active XR20M1280IL24TR-F QFN-24 4 -40C to +85C Active XR20M1280IL32-F QFN-32 8 -40C to +85C Active XR20M1280IL32TR-F QFN-32 8 -40C to +85C Active XR20M1280IL40-F QFN-40 16 -40C to +85C Active XR20M1280IL40TR-F QFN-40 16 -40C to +85C Active NOTE: TR = Tape and reel, F = Green / RoHS 2