XRT7295AT DS3/Sonet STS-1 Integrated Line Receiver December 2000-2 FEATURES APPLICATIONS D Fully Integrated Receive Interface for DS3 and D Interface to DS-3 Networks STS-1 Rate Signals D Digital Cross-Connect Systems D Integrated Equalization (Optional) and Timing D CSU/DSU Equipment Recovery D PCM Test Equipment D Loss-of-Signal and Loss-of-Lock Alarms D Fiber Optic Terminals D Variable Input Sensitivity Control D 5V Power Supply D Pin Compatible with XRT7295AE and XRT7295AC D Companion Device to T7296 Transmitter GENERAL DESCRIPTION The XRT7295AT DS3/SONET STS-1 integrated line settings, to adapt longer cables. High input sensitivity receiver is a fully integrated receive interface that allows for significant amounts of flat loss within the terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1 system. Figure 1 shows the block diagram of the device. (51.84Mbps) signal transmitted over coaxial cable. (See The XRT7295AT device is manufactured using linear Figure 13). CMOS technology. The XRT7295AT is available in a The device also provides the functions of receive 20-pin plastic SOJ package for surface mounting. equalization (optional), automatic-gain control (AGC), Two versions of the chip are available, one is for either clock-recovery and data retiming, loss-of-signal and DS3 or STS-1 operation (the XRT7295AT, this data loss-of-frequency-lock detection. The digital system sheet), and the other is for E3 operation (the XRT7295AE, interface is dual-rail, with received positive and negative refer to the XRT7295AE data sheet). Both versions are 1s appearing as unipolar digital signals on separate pin compatible. output leads. The on-chip equalizer is designed for cable distances of 0 to 450ft. from the cross-connect frame to For either DS3 or STS-1, an input reference clock at the device. The receive input has a variable input 44.736MHz or 51.84MHz provides the frequency sensitivity control, providing three different sensitivity reference for the device. ORDERING INFORMATION Operating Part No. Package Temperature Range XRT7295ATIW 20 Lead 300 Mil JEDEC SOJ -40C to + 85C Rev. 1.20 E2000 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538z (510) 668-7000z FAX (510) 668-7017XRT7295AT BLOCK DIAGRAM LPF1 LPF2 V A GNDA V D GNDD V C GNDC DD DD DD REQB 4 5 20 1 11 9 12 10 18 Loop Gain & Phase Slicers 2 Attenuator 14 VCO RCLK Equalizer Filter Detector R IN 16 RPDATA Retimer 15 RNDATA Peak Detector Digital LOS Detector Frequency Phase 19 AGC Aquisition Circuit LOSTHR 7 RLOS Analog LOS Analog Equalizer LOS Tuning Ckt. 17 3 6 13 8 ICT TMC1 TMC2 EXCLK RLOL Figure 1. Block Diagram Rev.1.20 2