xr XRT73L02M TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT MAY 2003 REV. 1.0.0 Provides low jitter clock outputs for either DS3,E3 GENERAL DESCRIPTION or STS-1 rates. The XRT73L02M is a two-channel fully integrated On-chip clock synthesizer provides the appropriate Line Interface Unit (LIU) for E3/DS3/STS-1 applica- rate clock from a single 12.288 MHz Clock. tions. It incorporates independent Receivers, Trans- mitters in a single 100 pin TQFP package. Provides low jitter output clock. The XRT73L02M can be configured to operate in ei- ther E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 TRANSMITTER: (51.84 MHz) modes.The transmitter can be turned off Compliant with Bellcore GR-499, GR-253 and ANSI or tri-stated for redundancy support and for conserv- T1.102 Specification for transmit pulse ing power. Tri-state Transmit output capability for redundancy The XRT73L02Ms differential receiver provides high applications noise interference margin and is able to receive the Transmitter can be turned on or off. data over 1000 feet of cable or with up to 12 dB of ca- ble attenuation. The XRT73L02M provides both Serial Microproces- CONTROL AND DIAGNOSTICS: sor Interface as well as Hardware mode for program- 5 wire Serial Microprocessor Interface for control ming and control. and configuration. The XRT73L02M supports local,remote and digital Supports optional internal Transmit Driver Monitor- loop-backs. The XRT73L02M also contains an on- ing. board Pseudo Random Binary Sequence (PRBS) PRBS error counter register to accumulate errors. generator and detector with the ability to insert and Hardware Mode for control and configuration. detect single bit error. Supports Local, Remote and Digital Loop-backs. Single 3.3 V 5% power supply. FEATURES 5 V Tolerant I/O. RECEIVER: Available in 100 pin TQFP. On chip Clock and Data Recovery circuit for high -40C to 85C Industrial Temperature Range. input jitter tolerance. APPLICATIONS Meets the jitter tolerance requirements as specified in ITU-T G.823 1993 for E3 and Telcordia GR-499- E3/DS3 Access Equipment. CORE for DS3 applications. STS1-SPE to DS3 Mapper. Detects and Clears LOS as per G.775. DSLAMs. Receiver Monitor mode handles up to 20 dB flat Digital Cross Connect Systems. loss with 6 dB cable attenuation. CSU/DSU Equipment. On chip B3ZS/HDB3 encoder and decoder that can Routers. either be enabled or disabled. Fiber Optic Terminals. On-chip clock synthesizer generates the appropri- ate rate clock from a single frequency XTAL. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT73L02M xr TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT FIGURE 1. BLOCK DIAGRAM OF THE XRT 73L02M SDI CLK OUT XRT75L03 SDO E3Clk,DS3Clk, Serial INT STS-1Clk Processor SClk Interface RLOL CS RxON RESET RxClkINV Clock HOST/HW Invert RxClk Peak Detector Synthesizer STS-1/DS3 E3 HDB3/ RPOS REQEN Clock & Data Slicer B3ZS AGC/ MUX RNEG/ RTIP Recovery Decoder Equalizer LCV RRING LOS SR/DR Remote Detector Local LoopBack RLB LLB LoopBack RLOS TTIP TPOS HDB3/ Line Tx B3ZS Driver Timing MUX TNEG Pulse TRING Encoder Control Shaping TxClk TAOS MTIP Device MRING Tx TxLEV Monitor Control TxON DMO Note: Serial Processor Interface input pins are shared by inHos Mode and redefined in theHardwar Mode. TRANSMIT INTERFACE CHARACTERISTICS RECEIVE INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Integrated Adaptive Receive Equalization for opti- Terminal Equipment and generates a bipolar signal mal Clock and Data Recovery. to the line Declares and Clears the LOS defect per ITU-T Integrated Pulse Shaping Circuit. G.775 requirements for E3 and DS3 applications. Built-in B3ZS/HDB3 Encoder (which can be dis- Meets Jitter Tolerance Requirements, as specified abled). in ITU-T G.823 1993 for E3 Applications. Accepts Transmit Clock with duty cycle of 30%- Meets Jitter Tolerance Requirements, as specified 70%. in Bellcore GR-499-CORE for DS3 Applications. Generates pulses that comply with the ITU-T G.703 Declares Loss of Signal (LOS) and Loss of Lock pulse template for E3 applications. (LOL) Alarms. Generates pulses that comply with the DSX-3 pulse Built-in B3ZS/HDB3 Decoder (which can be dis- template, as specified in Bellcore GR-499-CORE abled). and ANSI T1.102 1993. Recovered Data can be muted while the LOS Con- Generates pulses that comply with the STSX-1 dition is declared. pulse template, as specified in Bellcore GR-253- Outputs either Single-Rail or Dual-Rail data to the CORE. Terminal Equipment. Transmitter can be turned off in order to support redundancy designs. 2