XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR FEBRUARY 2004 REV. 1.0.2 GENERAL DESCRIPTION On-chip clock synthesizer provides the appropriate rate clock from a single 12.288 MHz Clock. The XRT75L00 is a single-channel fully integrated Provides low jitter output clock. Line Interface Unit (LIU) with Jitter Attenuator for E3/ DS3/STS-1 applications. It incorporates an independent Receiver, Transmitter and Jitter TRANSMITTER: Attenuator in a single 52 pin TQFP package. Compliant with Bellcore GR-499, GR-253 and ANSI The XRT75L00 can be configured to operate in either T1.102 Specification for transmit pulse E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz) modes. The transmitter can be turned off (tri- Tri-state Transmit output capability for redundancy stated) for redundancy support and for conserving applications power. Transmitter can be turned on or off. The XRT75L00s differential receiver provides high noise interference margin and is able to receive the JITTER ATTENUATOR: data over 1000 feet of cable or with up to 12 dB of cable attenuation. On chip advanced crystal-less Jitter Attenuator. The XRT75L00 incorporates an advanced crystal- Jitter Attenuator can be selected in Receive or less jitter attenuator that can be selected either in the Transmit paths. transmit or receive path. The jitter attenuator 16 or 32 bits selectable FIFO size. performance meets the ETSI TBR-24 and Bellcore GR-499 specifications. Meets the Jitter and Wander specifications The XRT75L00 provides both Serial Microprocessor described in T1.105.03b,ETSI TBR-24, Bellcore Interface as well as Hardware mode for programming GR-253 and GR-499 standards. and control. Jitter Attenuator can be disabled. The XRT75L00 supports local, remote and digital loop-backs. The XRT75L00 also contains an on- board Pseudo Random Binary Sequence (PRBS) CONTROL AND DIAGNOSTICS: generator and detector with the ability to insert and 5 wire Serial Microprocessor Interface for control detect single bit error. and configuration. Supports optional internal Transmit Driver Monitoring. FEATURES PRBS error counter register to accumulate errors. RECEIVER: Hardware Mode for control and configuration. On chip Clock and Data Recovery circuit for high input jitter tolerance. Supports Local, Remote and Digital Loop-backs. Meets E3/DS3/STS-1 Jitter Tolerance Single 3.3 V 5% power supply. Requirements. 5 V Tolerant I/O. Detects and Clears LOS as per G.775. Available in 52 pin TQFP. Meets Bellcore GR-499 CORE Jitter Transfer -40C to 85C Industrial Temperature Range. Requirements. Receiver Monitor mode handles up to 20 dB flat APPLICATIONS loss with 6 dB cable attenuation. E3/DS3 Access Equipment. Compliant with jitter transfer template outlined in DSLAMs. ITU G.751, G.752, G.755 and GR-499-CORE,1995 standards. Digital Cross Connect Systems. Meets ETSI TBR 24 Jitter Transfer Requirements. CSU/DSU Equipment. On chip B3ZS/HDB3 encoder and decoder that can Routers. be either enabled or disabled. Fiber Optic Terminals. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT75L00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.2 FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L00 SDI CLK OUT XRT75L03 SDO Serial ExClk/12M INT Processor SClk Interface RLOL CS RxON RESET RxClkINV Clock HOST/HW Invert RxClk Synthesizer Peak Detector STS-1/DS3 E3 HDB3/ RPOS REQEN Clock & Data Jitter AGC/ Slicer MUX B3ZS RNEG/ RTIP Recovery Attenuator Decoder Equalizer LCV RRING LOS SR/DR Remote Detector Local LoopBack RLB LLB LoopBack RLOS JATx/Rx TTIP TPData HDB3/ Line Tx Jitter Timing B3ZS Driver MUX TNData Pulse Attenuator TRING Encoder Control Shaping TxClk TAOS MTIP Device MRING Tx Monitor TxLEV Control TxON DMO Note: Serial Processor Interface input pins are shared by inHos Mode and redefined in theHardwar Mode. TRANSMIT INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line. Integrated Pulse Shaping Circuit. Built-in B3ZS/HDB3 Encoder (which can be disabled). Accepts Transmit Clock with duty cycle of 30%-70%. Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications. Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102 1993. Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE. Transmitter can be turned off in order to support redundancy designs. RECEIVE INTERFACE CHARACTERISTICS Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery. Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications. Meets Jitter Tolerance Requirements, as specified in ITU-T G.823 1993 for E3 Applications. Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications. Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms. Built-in B3ZS/HDB3 Decoder (which can be disabled). 2