XRT86L30 SINGLE T1/E1/J1 FRAMER/LIU COMBO JANUARY 2008 REV. 1.0.1 frames from the incoming T1/E1/J1 data stream and GENERAL DESCRIPTION write the contents into the Receive HDLC buffers. The XRT86L30 is a single channel 1.544 Mbit/s or The framer also contains a Transmit and Overhead 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated Data Input port, which permits Data Link Terminal 3 Equipment direct access to the outbound T1/E1/J1 solution featuring R technology (Relayless, frames. Likewise, a Receive Overhead output data Reconfigurable, Redundancy). The physical port permits Data Link Terminal Equipment direct interface is optimized with internal impedance, and access to the Data Link bits of the inbound T1/E1/J1 with the patented pad structure, the XRT86L30 frames. provides protection from power failures and hot swapping. The XRT86L30 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ The XRT86L30 contains an integrated DS1/E1/J1 E1.403-1999, ANSI T1/E1.231-1993, ANSI T1/ framer and LIU which provide DS1/E1/J1 framing and E1.408-1990, AT&T TR 62411 (12-90) TR54016, and error accumulation in accordance with ANSI/ITU T ITU G-703, G.704, G706 and G.733, AT&T Pub. specifications. The framer has a framing synchronizer 43801, and ETS 300 011, 300 233, JT G.703, JT and transmit-receive slip buffers. The slip buffers can G.704, JT G706, I.431. Extensive test and diagnostic be independently enabled or disabled as required functions include Loop-backs, Boundary scan, and can be configured to frame to the common DS1/ Pseudo Random bit sequence (PRBS) test pattern E1/J1 signal formats. generation, Performance Monitor, Bit Error Rate The Framer block contains a Transmit and Receive (BER) meter, forced error insertion, and LAPD T1/E1/J1 Framing function. There are 3 Transmit unchannelized data payload processing according to HDLC controllers which encapsulate contents of the ITU-T standard Q.921. Transmit HDLC buffers into LAPD Message frames. Applications and Features (next page) There are 3 Receive HDLC controllers which extract the payload content of Receive LAPD Message FIGURE 1. XRT86L30 1-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO External Data Link Controller Local PCM Highway XRT86L30 Tx Overhead In Rx Overhead Out 1:2 Turns Ratio TTIP 2-Frame Tx Serial Tx LIU Slip Buffer Tx Framer Data In Interface TRING Elastic Store Tx Serial Clock LLB LB 1:1 Turns Ratio RTIP 2-Frame Rx Serial Rx LIU Slip Buffer Rx Framer Data Out Interface RRING Elastic Store Rx Serial Clock LIU & PRBS HDLC/LAPD Performance Loopback Generator & RxLOS Controllers Monitor Analyser Control Line Side 8kHz sync OSC DMA Microprocessor Signaling & Interface JTAG Interface Alarms Back Plane 1.544-16.384 Mbit/s WR 4 3 ALE AS P System (Terminal) Side INT RD D 7:0 A 11:0 Select RDY DTACK TxON Intel/Motorola P Memory Configuration, Control & Status Monitor Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com ST-BUSXRT86L30 SINGLE T1/E1/J1 FRAMER/LIU COMBO REV. 1.0.1 APPLICATIONS High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems SONET/SDH terminal or Add/Drop multiplexers (ADMs) T1/E1/J1 add/drop multiplexers (MUX) Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 Digital Access Cross-connect System (DACs) Digital Cross-connect Systems (DCS) Frame Relay Switches and Access Devices (FRADS) ISDN Primary Rate Interfaces (PRA) PBXs and PCM channel bank T3 channelized access concentrators and M13 MUX Wireless base stations ATM equipment with integrated DS1 interfaces Multichannel DS1 Test Equipment T1/E1/J1 Performance Monitoring Voice over packet gateways Routers FEATURES Full duplex DS1 Tx and Rx Framer/LIU Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus (with stuffed dont care bits for the other 3 channels) Programmable output clocks for Fractional T1/E1/J1 Supports Channel Associated Signaling (CAS) Supports Common Channel Signalling (CCS) Supports ISDN Primary Rate Interface (ISDN PRI) signaling Extracts and inserts robbed bit signaling (RBS) 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) HDLC Controllers Support SS7 Timeslot assignable HDLC V5.1 or V5.2 Interface Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission Alarm Indication Signal with Customer Installation signature (AIS-CI) Remote Alarm Indication with Customer Installation (RAI-CI) Gapped Clock interface mode for Transmit and Receive. Intel/Motorola and Power PC interfaces for configuration, control and status monitoring Parallel search algorithm for fast frame synchronization Wide choice of T1 framing structures: SF/D4, ESF, SLC96, T1DM and N-Frame (non-signaling) 2