Features Fast read access time 55ns Low-power CMOS operation 100A max standby 35mA max active at 5MHz JEDEC standard packages 44-lead PLCC Direct upgrade from 512Kbit and 1Mbit (Atmel AT27C516 and AT27C1024) EPROMs 2Mb (128K x 16) 5V 10% supply One-time High-reliability CMOS technology 2,000V ESD protection Programmable, 200mA latchup immunity Read-only Memory Rapid programming algorithm 50s/word (typical) CMOS- and TTL-compatible inputs and outputs Integrated product identification code Atmel AT27C2048 Industrial temperature range 1. Description The Atmel AT27C2048 is a low-power, high-performance 2,097,152-bit, one-time pro- grammable, read-only memory (OTP EPROM) organized as 128K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 55 ns, eliminating the need for speed-reducing WAIT states. The x16 organization makes this part ideal for high-performance, 16- and 32-bit microprocessor systems. In read mode, the AT27C2048 typically consumes 15mA. Standby mode supply current is typically less than 10A The AT27C2048 is available in an industry-standard, JEDEC-approved, one-time program- mable (OTP) PLCC package. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems. With high-density, 128K word storage capability, the AT27C2048 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. The AT27C2048 has additional features that ensure high quality and efficient production use. The rapid programming algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50 s/word. The Inte- grated product identification code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper pro- gramming algorithms and voltages. 0632GEPROM4/112. Pin configurations 44-lead PLCC Pin name Function Top view A0 - A16 Addresses O0 - O15 Outputs CE Chip enable O12 7 39 A13 O11 8 38 A12 OE Output enable O10 9 37 A11 PGM Program strobe O9 10 36 A10 O8 11 35 A9 NC No connect GND 12 34 GND DC Dont connect NC 13 33 NC O7 14 32 A8 Note: Both GND pins must be O6 15 31 A7 connected. O5 16 30 A6 O4 17 29 A5 Note: PLCC package pins 1 and 23 are dont connect. 3. System considerations Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance. At a minimum, a 0.1F, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V and ground terminals of the device, as close to the device as possible. CC Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7F bulk electrolytic capacitor should be utilized, again connected between the V and ground terminals. This capacitor should be positioned as CC close as possible to the point where the power supply is connected to the array. Figure 3-1. Block diagram VCC DATA OUTPUTS GND O0 - O15 VPP OE OE, CE AND OUTPUT PROGRAM LOGIC BUFFERS CE Y DECODER Y-GATING A0 - A17 ADDRESS CELL MATRIX X DECODER INPUTS IDENTIFICATION 2 Atmel AT27C2048 0632GEPROM4/11 O3 18 6 O13 O2 19 5 O14 O1 20 4 O15 O0 21 3 CE OE 22 2 VPP DC 23 1 DC A0 24 44 VCC A1 25 43 PGM A2 26 42 A16 A3 27 41 A15 A4 28 40 A14