AT40K05, AT40K10, AT40K20, AT40K40 5K 50K Gates Coprocessor FPGA with FreeRAM DATASHEET Features Ultra high performance System speeds to 100MHz Array multipliers > 50MHz 10ns flexible SRAM Internal tri-state capability in each cell FreeRAM Flexible, single/dual port, synchronous/asynchronous 10ns SRAM 2,048 18,432 bits of distributed SRAM independent of logic cells 128 384 PCI compliant I/Os 5V capability Programmable output drive Fast, flexible array access facilitates pin locking Pin-compatible with XC4000 and XC5200 FPGAs Eight global clocks Fast, low skew clock distribution Programmable rising/falling edge transitions Distributed clock shutdown capability for low power management Global reset/asynchronous reset options 4 additional dedicated PCI clocks Cache Logic dynamic full/partial re-configurability in-system Unlimited re-programmability via serial or parallel modes Enables adaptive designs Enables fast vector multiplier updates Pin-compatible package options Thin, Plastic Quad Flat Packs (LQFP and PQFP) User-friendly design tools Timing driven placement and routing Automatic/Interactive multi-chip partitioning Fast, efficient synthesis Over 75 automatic component generators create 1000s of reusable, Fully Deterministic Logic and RAM functions Intellectual property cores Fir Filters, UARTs, PCI, FFT, and other system level functions Supply voltage 5V for AT40K Atmel-0896E-FPGA-AT40K05-10-20-40-Datasheet 062013(1) Table 1. AT40K Series Family Device AT40K05 AT40K10 AT40K20 AT40K40 Usable Gates 5K 10K 10K 20K 20K 30K 40K 50K Rows x Columns 16 x 16 24 x 24 32 x 32 48 x 48 Cells 256 576 1,024 2,304 (1) (1) (1) (1) Registers 256 576 1,024 2,304 RAM Bits 2,048 4,608 8,192 18,432 I/O (Maximum) 128 192 256 384 Note: 1. Packages with FCK will have eight less registers. 1. Description The AT40K is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10ns programmable synchronous/asynchronous, dual-port/single-port SRAM, eight global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC to 352-ball Square BGA, and support 5V designs for AT40K. The AT40K is designed to quickly implement high-performance, large gate count designs through the use of synthesis, and schematic-based tools used on a PC or Sun platform. Atmels design tools provide seamless integration with industry standard tools such as Synplicity, ModelSim, Exemplar and Viewlogic. The AT40K can be used as a coprocessor for high-speed (DSP/processor-based) designs by implementing a variety of computation intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution, and other multimedia applications. 1.1 Fast, Flexible and Efficient SRAM The AT40K FPGA offers a patented distributed 10ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmels macro generator tool. 1.2 Fast, Efficient Array, and Vector Multipliers The AT40Ks patented 8-sided core cell with direct horizontal, vertical, and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40K/AT40KLVs Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional FPGAs. 1.3 Cache Logic Design The AT40K, AT6000, and FPSLIC families are capable of implementing Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip replacing or complementing the active logic. The AT40K can act as a reconfigurable coprocessor. 2 Atmel AT40K Series FPGA DATASHEET Atmel-0896E-FPGA-AT40K05-10-20-40-Datasheet 062013