Features Ultra High Performance System Speeds to 100 MHz Array Multipliers > 50 MHz 10 ns Flexible SRAM Internal Tri-state Capability in Each Cell FreeRAM Flexible, Single/Dual Port, Synchronous/Asynchronous 10 ns SRAM 2,048 - 18,432 Bits of Distributed SRAM Independent of Logic Cells 128 - 384 PCI Compliant I/Os Programmable Output Drive 5K - 50K Gates Fast, Flexible Array Access Facilitates Pin Locking Pin-compatible with XC4000, XC5200 FPGAs Coprocessor 8 Global Clocks Fast, Low Skew Clock Distribution FPGA with Programmable Rising/Falling Edge Transitions Distributed Clock Shutdown Capability for Low Power Management FreeRAM Global Reset/Asynchronous Reset Options 4 Additional Dedicated PCI Clocks Cache Logic Dynamic Full/Partial Re-configurability In-System Unlimited Re-programmability via Serial or Parallel Modes AT40K05AL Enables Adaptive Designs Enables Fast Vector Multiplier Updates QuickChange Tools for Fast, Easy Design Changes AT40K10AL Pin-compatible Package Options Plastic Leaded Chip Carriers (PLCC) AT40K20AL Thin, Plastic Quad Flat Packs (LQFP, TQFP, PQFP) Industry-standard Design Tools AT40K40AL Seamless Integration (Libraries, Interface, Full Back-annotation) with Everest, Exemplar , Mentor , OrCAD , Synopsys , Verilog , Viewlogic , Synplicity Timing Driven Placement & Routing Automatic/Interactive Multi-chip Partitioning Fast, Efficient Synthesis Over 75 Automatic Component Generators Create 1000s of Reusable, Fully Deterministic Logic and RAM Functions Easy Migration to Atmel Gate Arrays for High Volume Production Supply Voltage 3.3V 5V I/O Tolerant Green (Pb/Halide-free/RoHS Compliant) Package Options Available 2818FFPGA07/06 1(1) Table 1. AT40KAL Family Device AT40K05AL AT40K10AL AT40K20AL AT40K40AL Usable Gates 5K - 10K 10K - 20K 20K - 30K 40K - 50K Rows x Columns 16 x 16 24 x 24 32 x 32 48 x 48 Cells 256 576 1,024 2,304 (1) (1) (1) (1) Registers 496 954 1,520 3,048 RAM Bits 2,048 4,608 8,192 18,432 I/O (Maximum) 128 192 256 384 Note: 1. Packages with FCK will have 8 less registers. Description The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), auto- matic component generators, and range in size from 5,000 to 50,000 usable gates. I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC to 352-ball Square BGA, and support 3.3V designs. The AT40KAL is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC or Sun platform. Atmels design tools provide seamless integration with industry standard tools such as Synplicity, ModelSim, Exemplar and Viewlogic. See the IDS Datasheet avail- able on the Atmel web site (