Features 80C51 Core Architecture 256 Bytes of On-chip RAM 1K Bytes of On-chip XRAM 32K Bytes of On-chip Flash Memory Data Retention: 10 Years at 85C Erase/Write Cycle: 100K Boot Code Section with Independent Lock Bits 2K Bytes of On-chip Flash for Bootloader In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability 2K Bytes of On-chip EEPROM Enhanced 8-bit Erase/Write Cycle: 100K 14-sources 4-level Interrupts Microcontroller Three 16-bit Timers/Counters Full Duplex UART Compatible 80C51 with CAN Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz) Five Ports: 32 + 2 Digital I/O Lines Controller and Five-channel 16-bit PCA with: PWM (8-bit) Flash Memory High-speed Output Timer and Edge Capture Double Data Pointer 21-bit Watchdog Timer (7 Programmable Bits) T89C51CC01 A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs Full CAN Controller: AT89C51CC01 Fully Compliant with CAN Rev2.0A and 2.0B Optimized Structure for Communication Management (Via SFR) 15 Independent Message Objects: Each Message Object Programmable on Transmission or Reception Individual Tag and Mask Filters up to 29-bit Identifier/Channel 8-byte Cyclic Data Register (FIFO)/Message Object 16-bit Status and Control Register/Message Object 16-bit Time-Stamping Register/Message Object CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object Access to Message Object Control and Data Registers Via SFR Programmable Reception Buffer Length Up To 15 Message Objects Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) Priority Management for Transmission Message Object Overrun Interrupt Supports: Time Triggered Communication Autobaud and Listening Mode Programmable Automatic Reply Mode (1) 1-Mbit/s Maximum Transfer Rate at 8 MHz Crystal Frequency in X2 Mode Readable Error Counters Programmable Link to On-chip Timer for Time Stamping and Network Synchronization Independent Baud Rate Prescaler Data, Remote, Error and Overload Frame Handling On-chip Emulation Logic (Enhanced Hook System) Power Saving Modes: Idle Mode Power-down Mode Rev. 4129NCAN03/08 1. At BRP = 1 sampling point will be fixed. 1 Power Supply: 3V to 5.5V Temperature Range: Industrial (-40 to +85C) Packages: VQFP44, PLCC44 TM Description The T89C51CC01 is the first member of the CANary family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC01 provides 32K Bytes of Flash memory including In-System-Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 1.2-Kbyte RAM. Special attention is paid to the reduction of the electro-magnetic emission of T89C51CC01. Block Diagram XTAL1 RAM Flash Boot EE XRAM PCA XTAL2 UART Timer 2 CAN 256x8 32kx loader PROM 1kx8 8 2kx8 2kx8 CONTROLLER ALE C51 CORE IB-bus PSEN CPU EA Timer 0 INT Parallel I/O Ports and Ext. Bus Watch 10 bit RD Ctrl Timer 1 Dog ADC Port 0Port 1 Port 2 Port 3Port 4 WR Notes: 1. 8 analog Inputs/8 Digital I/O 2. 2-Bit I/O Port 2 A/T89C51CC01 4129NCAN03/08 RESET T0 RxD T1 TxD INT0 INT1 Vcc P0 Vss P1(1) P2 P3 P4(2) ECI PCA VAREF T2EX VAVCC T2 VAGND RxDC TxDC