Features 80C51 Core Architecture 256 Bytes of On-chip RAM 256 Bytes of On-chip XRAM 16K Bytes of On-chip Flash Memory Data Retention: 10 Years at 85C Erase/Write Cycle: 100K Boot Code Section with Independent Lock Bits 2K Bytes of On-chip Flash for Bootloader In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability 2K Bytes of On-chip EEPROM Enhanced 8-bit Erase/Write Cycle: 100K 14-sources 4-level Interrupts Microcontroller Three 16-bit Timers/Counters Full Duplex UART Compatible 80C51 with CAN Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz) Three or Four Ports: 16 or 20 Digital I/O Lines Controller and Two-channel 16-bit PCA PWM (8-bit) Flash High-speed Output Timer and Edge Capture Double Data Pointer 21-bit Watchdog Timer (7 Programmable bits) T89C51CC02 A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs Full CAN Controller AT89C51CC02 Fully Compliant with CAN rev. 2.0A and 2.0B Optimized Structure for Communication Management (Via SFR) 4 Independent Message Objects -Each Message Object Programmable on Transmission or Reception -Individual Tag and Mask Filters up to 29-bit Identifier/Channel -8-byte Cyclic Data Register (FIFO)/Message Object -16-bit Status and Control Register/Message Object -16-bit Time-Stamping Register/Message Object -CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object -Access to Message Object Control and Data Registers Via SFR -Programmable Reception Buffer Length up to 4 Message Objects -Priority Management of Reception of Hits on Several Message Objects Simultaneously (Basic CAN Feature) -Priority Management for Transmission -Message Object Overrun Interrupt Supports -Time Triggered Communication -Autobaud and Listening Mode -Programmable Automatic Reply Mode (1) 1-Mbit/s Maximum Transfer Rate at 8 MHz Crystal Frequency In X2 Mode Readable Error Counters Programmable Link to On-chip Timer for Time Stamping and Network Synchronization Independent Baud Rate Prescaler Data, Remote, Error and Overload Frame Handling Power-saving Modes Idle Mode Power-down Mode Power Supply: 3 Volts to 5.5 Volts Temperature Range: Industrial (-40 to +85C) Packages: SOIC28, SOIC24, PLCC28, VQFP32 Rev. 4126LCAN01/08 Note: 1. At BRP = 1 sampling point will be fixed.TM Description Part of the CANary family of 8-bit microcontrollers dedicated to CAN network applica- tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller. In X2 Mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC02 provides 16K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 512 Bytes RAM. Special attention is payed to the reduction of the electro-magnetic emission of T89C51CC02. Block Diagram RAM Flash Boot EE XRAM PCA UART Timer 2 CAN 256x8 16K x loader PROM 256 x 8 8 2K x 8 2K x 8 CONTROLLER XTAL1 C51 CORE IB-bus XTAL2 CPU Timer 0 INT Parallel I/O Ports Watch 10-bit Ctrl Timer 1 Dog ADC Port 1 Port 2 Port 3 Port 4 Note: 1. 8 analog Inputs/8 Digital I/O. 2. 2-bit I/O Port. 2 AT/T89C51CC02 4126LCAN01/08 RESET T0 RxD T1 TxD INT0 INT1 Vcc Vss P1(1) P2(2) P3 P4(2) ECI PCA T2EX VAREF T2 VAVCC VAGND RxDC TxDC