Features 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory Data Retention: 10 Years at 85C Read/Write Cycle: 100K 2K Bytes of On-chip Flash for Bootloader 2K Bytes of On-chip EEPROM Read/Write Cycle: 100K Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply Enhanced 8-bit 14-sources 4-level Interrupts Three 16-bit Timers/Counters MCU with CAN Full Duplex UART Compatible 80C51 High-speed Architecture Controller and In Standard Mode: 40 MHz (Vcc 3V to 5.5V, both Internal and external code execution) Flash Memory 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) In X2 mode (6 Clocks/machine cycle) 20 MHz (Vcc 3V to 5.5V, both Internal and external code execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) AT89C51CC03 Five Ports: 32 + 4 Digital I/O Lines Five-channel 16-bit PCA with PWM (8-bit) High-speed Output Timer and Edge Capture Double Data Pointer 21-bit WatchDog Timer (7 Programmable Bits) A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs SPI Interface, (PLCC52 and VPFP64 packages only) Full CAN Controller Fully Compliant with CAN Rev 2.0A and 2.0B Optimized Structure for Communication Management (Via SFR) 15 Independent Message Objects Each Message Object Programmable on Transmission or Reception Individual Tag and Mask Filters up to 29-bit Identifier/Channel 8-byte Cyclic Data Register (FIFO)/Message Object 16-bit Status and Control Register/Message Object 16-bit Time-Stamping Register/Message Object CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object Access to Message Object Control and Data Registers Via SFR Programmable Reception Buffer Length Up To 15 Message Objects Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) Priority Management for Transmission Message Object Overrun Interrupt Supports Time Triggered Communication Autobaud and Listening Mode Programmable Automatic Reply Mode (1) Crystal Frequency in X2 Mode 1-Mbit/s Maximum Transfer Rate at 8 MHz Readable Error Counters Programmable Link to On-chip Timer for Time Stamping and Network Synchronization Independent Baud Rate Prescaler Data, Remote, Error and Overload Frame Handling Rev. 4182OCAN09/08 1. At BRP = 1 sampling point will be fixed. On-chip Emulation Logic (Enhanced Hook System) Power Saving Modes Idle Mode Power-down Mode Power Supply: 3 volts to 5.5 volts Temperature Range: Industrial (-40 to +85C), Automotive (-40C to +125C) Packages: VQFP44, PLCC44, VQFP64, PLCC52 Description The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller AT89C51CC03 provides 64K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 2048 byte ERAM. Primary attention is paid to the reduction of the electro-magnetic emission of AT89C51CC03. Block Diagram XTAL1 RAM Flash Boot EE ERAM PCA XTAL2 UART Timer2 CAN 256x8 64k x 8 loader PROM 2048 2kx8 2kx8 CONTROLLER ALE C51 CORE IB-bus PSEN CPU EA Timer 0 INT Parallel I/O Ports and Ext. Bus Watch Emul 10 bit SPI RD Timer 1 Ctrl Dog Unit Interface ADC Port 0Port 1 Port 2 Port 3Port 4 WR Notes: 1. 8 analog Inputs/8 Digital I/O 2. 5-Bit I/O Port 2 AT89C51CC03 4182OCAN09/08 RESET T0 RxD T1 TxD INT0 INT1 Vcc P0 Vss P1(1) P2 P3 P4(2) ECI PCA T2EX T2 RxDC MOSI SCK MISO TxDC