Features Compatible with MCS 51 Products 20 MIPS Throughput at 20 MHz Clock Frequency and 2.4V, 85C Operating Conditions Single Clock Cycle per Byte Fetch 2/4K Bytes of In-System Programmable (ISP) Flash Memory Serial Interface for Program Downloading 32-byte Fast Page Programming Mode 32-byte User Signature Array 2.4V to 5.5V V Operating Range CC 8-bit Fully Static Operation: 0 Hz to 20 MHz 2-level Program Memory Lock Microcontroller 256 x 8 Internal RAM Hardware Multiplier with 2/4-Kbyte 15 Programmable I/O Lines Configurable I/O with Quasi-bidirectional, Input, Push-pull Output, and Flash Open-drain Modes Enhanced UART with Automatic Address Recognition and Framing Error Detection Enhanced SPI with Double-buffered Send/Receive AT89LP2052 Programmable Watchdog Timer with Software Reset 4-level Interrupt Priority AT89LP4052 Analog Comparator with Selectable Interrupt and Debouncing Two 16-bit Enhanced Timer/Counters with 8-bit PWM Brown-out Detector and Power-off Flag Internal Power-on Reset Low Power Idle and Power-down Modes Interrupt Recovery from Power-down Mode 1. Description The AT89LP2052/LP4052 is a low-power, high-performance CMOS 8-bit microcon- troller with 2/4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel s high-density nonvolatile memory technology and is com- patible with the industry-standard MCS-51 instruction set. The AT89LP2052/LP4052 is built around an enhanced CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch required 6 clock cycles, forc- ing instructions to execute in 12, 24 or 48 clock cycles. In the AT89LP2052/LP4052 CPU, instructions need only 1 to 4 clock cycles providing 6 to 12 times more through- put than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current consump- tion. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption. 3547JMICRO10/09The two timer/counters in the AT89LP2052/LP4052 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition both timer/counters may be configured as 8-bit Pulse Width Modulators with 8-bit prescalers. The I/O ports of the AT89LP2052/LP4052 can be independently configured in one of four oper- ating modes. In quasi-bidirectional mode, the ports operate as in the classic 8051. In input mode, the ports are tri-stated. Push-pull output mode provides full CMOS drivers and open-drain mode provides just a pull-down. 2. Pin Configuration 2.1 20-lead PDIP/SOIC/TSSOP (VPP) RST 1 20 VCC (RXD) P3.0 2 19 P1.7 (SCK) (TXD) P3.1 3 18 P1.6 (MISO) XTAL2 4 17 P1.5 (MOSI) XTAL1 5 16 P1.4 (SS) (INT0) P3.2 6 15 P1.3 (INT1) P3.3 7 14 P1.2 (T0) P3.4 8 13 P1.1 (AIN1) (T1) P3.5 9 12 P1.0 (AIN0) GND 10 11 P3.7 (SYSCLK) 2 AT89LP2052/LP4052 3547JMICRO10/09