Features
High-performance, Low-power AVR 8-bit Microcontroller
Advanced RISC Architecture
130 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
8K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
8-bit
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
Microcontroller
True Read-While-Write Operation
512 Bytes EEPROM
with 8K Bytes
Endurance: 100,000 Write/Erase Cycles
512 Bytes Internal SRAM
In-System
Programming Lock for Software Security
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
Programmable
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Flash
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC
8 Single-ended Channels
ATmega8535
7 Differential Channels for TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP
ATmega8535L
Package Only
Byte-oriented Two-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Summary
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
I/O and Packages
32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF
Operating Voltages
2.7 - 5.5V for ATmega8535L
4.5 - 5.5V for ATmega8535
Speed Grades
0 - 8 MHz for ATmega8535L
0 - 16 MHz for ATmega8535
2502KSAVR10/06
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.Pin Configurations Figure 1. Pinout ATmega8535
(XCK/T0) PB0 PA0 (ADC0)
(T1) PB1 PA1 (ADC1)
(INT2/AIN0) PB2 PA2 (ADC2)
(OC0/AIN1) PB3 PA3 (ADC3)
(SS) PB4 PA4 (ADC4)
(MOSI) PB5
PA5 (ADC5)
(MISO) PB6
PA6 (ADC6)
(SCK) PB7
PA7 (ADC7)
RESET
AREF
VCC
GND
GND
AVCC
XTAL2
PC7 (TOSC2)
XTAL1
PC6 (TOSC1)
(RXD) PD0 PC5
(TXD) PD1 PC4
(INT0) PD2 PC3
(INT1) PD3 PC2
(OC1B) PD4 PC1 (SDA)
(OC1A) PD5 PC0 (SCL)
(ICP1) PD6 PD7 (OC2)
PLCC
(MOSI) PB5 1 33 PA4 (ADC4)
(MOSI) PB5 7 39 PA4 (ADC4)
(MISO) PB6 2 32 PA5 (ADC5)
(MISO) PB6 8 38 PA5 (ADC5)
(SCK) PB7 3 31 PA6 (ADC6)
(SCK) PB7 9 37 PA6 (ADC6)
RESET 4 30 PA7 (ADC7)
RESET 10 36 PA7 (ADC7)
VCC 5 29 AREF
VCC 11 35 AREF
GND 6 28 GND
GND 12 34 GND
XTAL2 7 27 AVCC
XTAL2 13 33 AVCC
XTAL1 8 26 PC7 (TOSC2)
XTAL1 14 32 PC7 (TOSC2)
(RXD) PD0 9 25 PC6 (TOSC1)
(RXD) PD0 15 31 PC6 (TOSC1)
(TXD) PD1 10 24 PC5
(TXD) PD1 16 30 PC5
(INT0) PD2 11 23 PC4
(INT0) PD2 17 29 PC4
NOTE: MLF Bottom pad should be soldered to ground.
Disclaimer Typical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
2
ATmega8535(L)
2502KSAVR10/06
(INT1) PD3 12 44 PB4 (SS)
(OC1B) PD4 13 43 PB3 (AIN1/OC0)
(OC1A) PD5 14 42 PB2 (AIN0/INT2)
(ICP1) PD6 15 41 PB1 (T1)
(OC2) PD7 16 40 PB0 (XCK/T0)
VCC 17 39 GND
GND 18 38 VCC
(SCL) PC0 19 37 PA0 (ADC0)
(SDA) PC1 20 36 PA1 (ADC1)
PC2 21 35 PA2 (ADC2)
PC3 22 34 PA3 (ADC3)
(INT1) PD3 18 6 PB4 (SS)
(OC1B) PD4 19 5 PB3 (AIN1/OC0)
(OC1A) PD5 20 4 PB2 (AIN0/INT2)
(ICP1) PD6 21 3 PB1 (T1)
(OC2) PD7 22 2 PB0 (XCK/T0)
VCC 23 1 GND
GND 24 44 VCC
(SCL) PC0 25 43 PA0 (ADC0)
(SDA) PC1 26 42 PA1 (ADC1)
PC2 27 41 PA2 (ADC2)
PC3 28 40 PA3 (ADC3)