Features Utilizes the AVR RISC Architecture High-performance and Low-power 8-bit RISC Architecture 90 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Up to 8 MIPS Throughput at 8 MHz Nonvolatile Program and Data Memory 1K Byte of Flash Program Memory In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12) 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12 8-bit Endurance: 100,000 Write/Erase Cycles Programming Lock for Flash Program and EEPROM Data Security Microcontroller Peripheral Features Interrupt and Wake-up on Pin Change with 1K Byte One 8-bit Timer/Counter with Separate Prescaler On-chip Analog Comparator Flash Programmable Watchdog Timer with On-chip Oscillator Special Microcontroller Features Low-power Idle and Power-down Modes External and Internal Interrupt Sources ATtiny11 In-System Programmable via SPI Port (ATtiny12) Enhanced Power-on Reset Circuit (ATtiny12) Internal Calibrated RC Oscillator (ATtiny12) ATtiny12 Specification Low-power, High-speed CMOS Process Technology Fully Static Operation Power Consumption at 4 MHz, 3V, 25C Summary Active: 2.2 mA Idle Mode: 0.5 mA Power-down Mode: <1 A Packages 8-pin PDIP and SOIC Operating Voltages 1.8 - 5.5V for ATtiny12V-1 2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4 4.0 - 5.5V for ATtiny11-6 and ATtiny12-8 Speed Grades 0 - 1.2 MHz (ATtiny12V-1) 0 - 2 MHz (ATtiny11L-2) 0 - 4 MHz (ATtiny12L-4) 0 - 6 MHz (ATtiny11-6) 0 - 8 MHz (ATtiny12-8) Pin Configuration ATtiny11 ATtiny12 PDIP/SOIC PDIP/SOIC Not recommended for new (RESET) PB5 1 8 VCC (RESET) PB5 1 8 VCC design (XTAL1) PB3 2 7 PB2 (SCK/T0) (XTAL1) PB3 2 7 PB2 (T0) (XTAL2) PB4 3 6 PB1 (MISO/INT0/AIN1) (XTAL2) PB4 3 6 PB1 (INT0/AIN1) GND 4 5 PB0 (AIN0) GND 4 5 PB0 (MOSI/AIN0) Rev. 10 1006FS06FSAVR0AVR06/06/077 Note: This is a summary document. A complete document 1 is available on our Web site at www.atmel.com.Overview The ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny11/12 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working regis- ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Table 1. Parts Description Device Flash EEPROM Register Voltage Range Frequency ATtiny11L 1K - 32 2.7 - 5.5V 0-2 MHz ATtiny11 1K - 32 4.0 - 5.5V 0-6 MHz ATtiny12V 1K 64 B 32 1.8 - 5.5V 0-1.2 MHz ATtiny12L 1K 64 B 32 2.7 - 5.5V 0-4 MHz ATtiny12 1K 64 B 32 4.0 - 5.5V 0-8 MHz The ATtiny11/12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2 ATtiny11/12 1006FSAVR06/07