Features Utilizes the AVR RISC Architecture AVR High-performance and Low-power RISC Architecture 90 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General-purpose Working Registers Up to 4 MIPS Throughput at 4 MHz Nonvolatile Program Memory 2K Bytes of Flash Program Memory Endurance: 1,000 Write/Erase Cycles Programming Lock for Flash Program Data Security Peripheral Features 8-bit Interrupt and Wake-up on Low-level Input One 8-bit Timer/Counter with Separate Prescaler Microcontroller On-chip Analog Comparator Programmable Watchdog Timer with On-chip Oscillator with 2K Bytes of Built-in High-current LED Driver with Programmable Modulation Special Microcontroller Features Flash Low-power Idle and Power-down Modes External and Internal Interrupt Sources Power-on Reset Circuit with Programmable Start-up Time Internal Calibrated RC Oscillator ATtiny28L Power Consumption at 1 MHz, 2V, 25C Active: 3.0 mA Idle Mode: 1.2 mA ATtiny28V Power-down Mode: <1 A I/O and Packages 11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver 28-lead PDIP, 32-lead TQFP, and 32-pad MLF Summary Operating Voltages V : 1.8V - 5.5V for the ATtiny28V CC V : 2.7V - 5.5V for the ATtiny28L CC Speed Grades 0 - 1.2 MHz for the ATtiny28V 0 - 4 MHz For the ATtiny28L Pin Configurations PDIP TQFP/QFN/MLF RESET 1 28 PA0 PD0 2 27 PA1 PD1 3 26 PA3 PD2 4 25 PA2 (IR) 24 PB7 PD3 1 PD3 5 24 PB7 PD4 2 23 PB6 PD4 6 23 PB6 NC 3 22 NC VCC 7 22 GND VCC 4 21 GND 20 NC GND 5 GND 8 21 NC NC 6 19 NC XTAL1 9 20 VCC XTAL1 7 18 VCC XTAL2 10 19 PB5 XTAL2 8 17 PB5 PD5 11 18 PB4 (INT1) PD6 12 17 PB3 (INT0) PD7 13 16 PB2 (T0) (AIN0) PB0 14 15 PB1 (AIN1) Rev. 1062FSAVR07/06 Note: This is a summary document. A complete document 1 is available on our Web site at www.atmel.com. PD5 9 32 PD2 PD6 10 31 PD1 PD7 11 30 PD0 (AIN0) PB0 12 29 RESET (AIN1) PB1 13 28 PA0 (T0) PB2 14 27 PA1 (INT0) PB3 15 26 PA3 (INT1) PB4 16 25 PA2 (IR)Description The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi- tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly con- nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architec- ture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. Block Diagram Figure 1. The ATtiny28 Block Diagram VCC XTAL1 XTAL2 INTERNAL 8-BIT DATA BUS CALIBRATED INTERNAL OSCILLATOR OSCILLATOR OSCILLATOR GND RESET PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL MCU CONTROL PROGRAM HARDWARE REGISTER FLASH STACK TIMER/ INSTRUCTION GENERAL COUNTER REGISTER PURPOSE REGISTERS INTERRUPT INSTRUCTION Z UNIT DECODER CONTROL ALU LINES STATUS REGISTER HARDWARE MODULATOR PROGRAMMING LOGIC DATA REGISTER DATA REGISTER DATA DIR DATA REGISTER PORTA CONTROL PORTA PORTB PORTD REG. PORTD REGISTER PORTB PORTD PORTA The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counter and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or inter- 2 ATtiny28L/V 1062FSAVR07/06 + - ANALOG COMPARATOR