CD-700 Complete VCXO Based Phase Lock Loop CD-700 Description The VI CD-700 is a user-con gurable crystal based PLL integrated circuit. It includes a digital phase detector, op-amp, VCXO and additional integrated functions for use in digital synchronization applications. Loop lter software is available as well SPICE models for circuit simulation. Features Applications 5 x 7.5 x 2 mm, smallest VCXO PLL available Frequency Translation Output Frequencies to 77.76 MHz Clock Smoothing, Clock Switching 5.0 or 3.3 Vdc operation NRZ Clock recovery Tri-State Output DSLAM, ADM, ATM, Aggregation, Optical Switching/Routing, Holdover on Loss of Signal Alarm Base Station VCXO with CMOS outputs Synchronous Ethernet 0/70 or 40/85C temperature range Low jitter PLLs Hermetically sealed ceramic SMD package Product is compliant to RoHS directive Block Diagram LOS PHO OPN OPOUT VC LOSIN (8) (3) (2) (1) (16) (4) DATAIN (5) OUT1 VCXO Phase Detector and (13) LOS CLKIN (6) OUT2 Optional 2nd divider (11) RCLK RDATA OPP GND VDD HIZ (9) (10) (15) (7) (14) (12) Page 1 of 12Performance Speci cations Table 1. Electrical Performance Parameter Symbol Min Typical Maximum Units Output Frequency (ordering option) OUT 1, 5.0 V option 1.000 77.760 MHz OUT 1, 3.3 V option 1.000 77.760 MHz 1 Supply Voltage +5.0 V 4.5 5.0 5.5 V DD +3.3 2.97 3.3 3.63 V Supply Current I 63 mA DD Output Logic Levels 2 Output Logic High V 2.5 V OH 2 Output Logic Low V 0.5 V OL Output Transition Times 2 Rise Time t 3.0 ns R 2 Fall Time t 3.0 ns F Input Logic Levels 2 Input Logic High V 2.0 V IH 2 Input Logic Low V 0.5 V IL Loss of Signal Indication 2 Output Logic High V 2.5 V OH 2 Output Logic Low V 0.5 V OL Nominal Frequency on Loss of Signal Output 1 75 ppm Output 2 75 ppm 3 Symmetry or Duty Cycle Out 1 SYM1 40/60 % Out 2 SYM2 45/55 % RCLK RCLK 40/60 % Absolute Pull Range (ordering option) APR 50 ppm over operating temperure, aging, and power 80 supply variations 100 Test Conditions for APR (+5.0 V option) V 0.5 4.5 V C Test Conditions for APR (+3.3 V option) V 0.3 3.0 V C Gain Transfer Kv Positive Phase Detector Gain Kv +5.0 V option 0.53 rad/V +3.3 V option 0.35 rad/V Operating temperature (ordering option) T 0/70 or -40/85 C OP Control Voltage Leakage Current I 1.0 A VCXO 1. A 0.01uF and 0.1uF parallel capacitor should be located as close to pin 14 as possible (and grounded). 2. Figure 2 de nes these parameters. Figure 3 illustrates the equivalent ve gate TTL load and operating conditions under which these parameters are tested and speci ed. Loads greater than 15 pF will adversely e ect rise/fall time as well as symmetry. 3. Symmetry is de ned as (ON TIME/PERIOD with Vs=1.4 V for both 5.0 V and 3.3 V operation. Figure 2. Output Waveform Figure 3. OUT1, OUT2, RCLK, RDATA Test Conditions (25 5 C) Page 2 of 12