Short Form Data Sheet April 2012 DS31404 4-Input, 8-Output, Dual DPLL Timing IC with Sub-ps Output Jitter General Description Features Four Input Clocks The DS31404 is a flexible, high-performance timing IC for diverse frequency conversion and frequency Differential or CMOS/TTL Format synthesis applications. On each of its four input clocks Any Frequency from 2kHz to 750MHz and eight output clocks, the device can accept or Fractional Scaling for 64B/66B and FEC generate nearly any frequency between 2kHz and Scaling (e.g., 64/66, 237/255, 238/255) or Any 750MHz. The device offers two independent DPLLs to Other Downscaling Requirement serve two independent clock-generation paths. Continuous Input Clock Quality Monitoring Automatic or Manual Clock Selection The input clocks are divided down, fractionally scaled as Three 2/4/8kHz Frame Sync Inputs needed, and continuously monitored for activity and Two High-Performance DPLLs frequency accuracy. The best input clock is selected, Hitless Reference Switching on Loss of Input manually or automatically, as the reference clock for Automatic or Manual Phase Build-Out each of the two flexible, high-performance digital PLLs. Holdover on Loss of All Inputs Each DPLL lock to the selected reference and provides Programmable Bandwidth, 0.5mHz to 400Hz programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input Four Digital Frequency Synthesizers clocks. The digital PLLs are followed by a clock Each Can Slave to Either DPLL synthesis subsystem that has four fully programmable Produce Any 2kHz Multiple Up to 77.76MHz digital frequency synthesis blocks, two high-speed low- Per-DFS Clock Phase Adjust jitter APLLs, and eight output clocks, each with its own Two Output APLLs 32-bit divider and phase adjustment. The APLLs provide Output Frequencies to 750MHz fractional scaling and output jitter less than 1ps RMS. High Resolution Fractional Scaling for FEC For telecom systems, the DS31404 has all required and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement features and functions to serve as a central timing Less than 1ps RMS Output Jitter function or as a line card timing IC. With a suitable Simultaneously Produce Two Low-Jitter Rates oscillator the DS31404 meets the requirements of from the Same Reference (e.g., 622.08MHz Stratum 2, 3E, 3, 4E, and 4, G.812 Types IIV, G.813, for SONET and 156.25MHz for 10GE) and G.8262. Eight Output Clocks in Four Groups Nearly Any Frequency from < 1Hz to 750MHz Applications Each Group Slaves to a DFS Clock, Any APLL Frequency Conversion Applications in a Wide Variety of Clock, or Any Input Clock (Divided and Scaled) Equipment Types Each Has a Differential Output (2 CML, 2 Telecom Line Cards or Timing Cards with Any Mix of LVDS/LVPECL) and Separate CMOS/TTL Output SONET/SDH, Synchronous Ethernet and/or OTN 32-Bit Frequency Divider Per Output Ports in WAN Equipment Including MSPPs, Ethernet Two Sync Pulse Outputs: 8kHz and 2kHz Switches, Routers, DSLAMs, and Base Stations General Features Suitable Line Card IC or Timing Card IC for Ordering Information Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU PART TEMP RANGE PIN-PACKAGE Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, DS31404GN+ -40 C to +85 C 256 CSBGA NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, +Denotes a lead(Pb)-free/RoHS-compliant package. 125M, 156.25M, and Nx19.44M Up to 622.08M SPI is a trademark of Motorola, Inc. Internal Compensation for Local Oscillator Frequency Error SPI Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) 1 Short Form Data Sheet DS31404 Application Example clock monitoring and selection, hitless switching, holdover, frequency conversion, fractional scaling, jitter attenuation 19.44MHz, 38.88MHz, 25MHz, etc. DS31404 IC1 system timing OC1, OC2 clocks to line card SERDES n DPLL1 Path from master and slave SONET/SDH, 1GE, 10GE, OTN, FC, etc. IC2 timing cards 3 unrelated frequencies simultaneously at <1ps rms jitter plus other frequencies at somewhat higher jitter OC4 line timing recovered line clocks from SERDES n IC3, IC4 SONET/SDH, 1GE, 10GE, OTN, FC etc. DPLL2 Path to master and slave OC5 frequencies can be unrelated to one another timing cards 8kHz, 19.44MHz, 155.52M, 622.08M, 25M, 38.88MHz, 25MHz, etc. 125M, 156.25M, etc. with or without fractional scaling for clock monitoring and selection, FEC, 64B/66B, etc. undo fractional scaling, MANY other rates possible, frequency conversion including DS1, E1, DS3, E3, 10M and Nx19.44M. 2