Supertex inc. HV2701 Low Charge Injection 16-Channel High Voltage Analog Switch with Bleed Resistors Features General Description HVCMOS technology for high performance The Supertex HV2701 is a low charge injection, 16-channel, high Integrated bleed resistors on the outputs voltage, analog switch integrated circuit (IC) with bleed resistors. 16-channel high voltage analog switch The device can be used in applications requiring high voltage 3.3V input logic level compatible switching controlled by low voltage control signals, such as medical 20MHz data shift clock frequency ultrasound imaging and piezoelectric transducer drivers. The bleed Very low quiescent power dissipation (-10A) resistors eliminate voltage built up on capacitive loads such as Low parasitic capacitance piezoelectric transducers. DC to 50MHz small signal frequency response -60dB typical OFF-isolation at 5.0MHz Input data are shifted into a 16-bit shift register that can then be CMOS logic circuitry for low power retained in a 16-bit latch. To reduce any possible clock feed-through Excellent noise immunity noise, the latch enable bar should be left high until all bits are Cascadable serial data register with latches clocked in. Data is clocked in during the rising edge of the clock. Flexible operating supply voltages Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. Applications Medical ultrasound imaging The device is suitable for various combinations of high voltage NDT metal flaw detection supplies, e.g., V /V : +40V/-160V, +100V/-100V, and +160V/-40V. Piezoelectric transducer drivers PP NN Optical MEMS modules Block Diagram Level Output Latches Shifters Switches D LE SW0 CLR D SW1 LE CLR DIN D 16-Bit SW2 LE Shift CLR CLK Register DOUT D SW14 LE CLR D SW15 LE CLR VDD GND LE CLR VNN VPP RGND Doc. DSFP-HV2701 Supertex inc. E012412 www.supertex.comHV2701 Pin Configurations Ordering Information Package Options 3 2 1 7 6 5 4 42-Ball Bumped Die 48-Lead LQFP 48-Ball fpBGA 13 12 11 10 9 8 Device 16 5.29x5.30mm body 7.00x7.00mm body 7.00x8.00mm body 18 17 15 14 1.01mm height (max) 1.60mm height (max) 1.20mm height (max) 22 21 20 19 0.52 / 0.60mm pitch 0.50mm pitch 0.75mm pitch 26 25 24 23 34 33 32 31 30 29 28 27 HV2701 HV2701BD M936 HV2701FG-G HV2701GA-G 42 41 40 39 38 37 36 35 -G indicates package is RoHS compliant (Green). Bumped Die package is RoHS compliant (Green). 42-Ball Bumped Die (BD) M936 specifies product in tape and reel. (top view) 48 Absolute Maximum Ratings 1 Parameter Value V logic supply -0.5V to +7.0V DD V -V differential supply 220V PP NN V positive supply -0.5V to V +200V PP NN V negative supply +0.5V to -200V NN Logic input voltage -0.5V to V +0.3V 48-Lead LQFP (FG) DD (top view) Analog signal range V to V NN PP 1 2 3 4 5 6 Peak analog signal current/channel 3.0A A Storage temperature -65C to 150C B C Power dissipation: D 42-Ball Bumped Die (BD) 1.5W E 48-Lead LQFP (FG) 1.0W F 48-Ball fpBGA (GA) 1.0W G H Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 48-Ball fpBGA (GA) (top view) Recommended Operating Conditions Product Marking Sym Parameter Value LLLLLLL YY = Year Sealed YYWW V Logic power supply voltage 3.0V to 5.5V WW = Week Sealed DD HV2701BD L = Lot Number V Positive high voltage supply +40V to V +200V PP NN Package may or may not include the following marks: Si or V Negative high voltage supply -40V to -160V NN 42-Ball Bumped Die (BD) V High level input voltage 0.9V to V Top Marking IH DD DD V Low level input voltage 0V to 0.1V YY = Year Sealed IL DD YYWW HV2701FG WW = Week Sealed LLLLLLLLL Analog signal voltage L = Lot Number V V +10V to V -10V SIG NN PP peak-to-peak C = Country of Origin* Bottom Marking A = Assembler ID* T Operating free air temperature 0C to 70C A = Green Packaging CCCCCCCC Notes: AAA *May be part of top marking 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. Package may or may not include the following marks: Si or 2. V must be within V and V or floating during power up/down transition. SIG NN PP 48-Lead LQFP (FG) 3. Rise and fall times of power supplies V , V , and V should not be less than DD PP NN 1.0msec. YY = Year Sealed YYWW WW = Week Sealed HV2701GA L = Lot Number LLLLLLLLL = Green Packaging Packages may or may not include the following marks: Si or 48-Ball fpBGA (GA) Doc. DSFP-HV2701 Supertex inc. E012412 www.supertex.com 2