KSZ8565R 5-Port 10/100 Ethernet Switch with Audio Video Bridging and Single RGMII/MII/RMII Interface Four Integrated PHY Ports Highlights - 100BASE-TX/10BASE-T/Te IEEE 802.3 Non-blocking wire-speed Ethernet switching fabric - Fast Link-up option significantly reduces link-up time Full-featured forwarding and filtering control, includ- - Auto-negotiation and Auto-MDI/MDI-X support ing Access Control List (ACL) filtering - Energy-Efficient Ethernet (EEE) support with low- Full VLAN and QoS support power idle mode and clock stoppage - On-chip termination resistors and internal biasing for Four ports with integrated 10/100BASE-T PHY trans- differential pairs to reduce power ceivers with optional Quiet-WIRE EMC filtering Advanced Switch Capabilities One port with 10/100/1000 Ethernet MAC and con- - IEEE 802.1Q VLAN support for 128 active VLAN figurable RGMII/MII/RMII interface groups and the full range of 4096 VLAN IDs IEEE 1588v2 Precision Time Protocol (PTP) support - IEEE 802.1p/Q tag insertion/removal on per port basis IEEE 802.1AS/Qav Audio Video Bridging (AVB) - VLAN ID on per port or VLAN basis IEEE 802.3az Energy Efficient Ethernet (EEE) - IEEE 802.3x full-duplex flow control and half-duplex IEEE 802.1X access control support back pressure collision control EtherGreen power management features, - IEEE 802.1X access control (Port and MAC address) including low power standby - IGMP v1/v2/v3 snooping for multicast packet filtering 2 Flexible management interface options: SPI, I C, - IPv6 multicast listener discovery (MLD) snooping MIIM, and in-band management via any port - IPv4/IPv6 QoS support, QoS/CoS packet prioritization Extended Auto temperature range support - 802.1p QoS packet classification with 4 priority queues - Programmable rate limiting at ingress/egress ports 128-pin TQFP-EP (14 x 14mm) RoHS compliant pkg IEEE 1588v2 PTP and Clock Synchronization - Transparent Clock (TC) with auto correction update Target Applications - Master and slave Ordinary Clock (OC) support Industrial Ethernet (Profinet, MODBUS, Ethernet/IP) - End-to-end (E2E) or peer-to-peer (P2P) Real-time Ethernet networks - PTP multicast and unicast message support - PTP message transport over IPv4/v6 and IEEE 802.3 IEC 61850 networks w/ power substation automation - IEEE 1588v2 PTP packet filtering Industrial control/automation switches - Synchronous Ethernet support via recovered clock Networked measurement and control systems Audio Video Bridging (AVB) Test and measurement equipment - Compliant with IEEE 802.1BA/AS/Qat/Qav standards - Priority queuing, Low latency cut-through mode Features - gPTP time synchronization, credit-based traffic shaper - Time aware traffic scheduler per port Switch Management Capabilities - 10/100Mbps Ethernet switch basic functions: frame Comprehensive Configuration Registers Access buffer management, address look-up table, queue 2 - High-speed 4-wire SPI (up to 50MHz), I C interfaces management, MIB counters provide access to all internal registers - Non-blocking store-and-forward switch fabric assures - MII Management (MIIM, MDC/MDIO 2-wire) Interface fast packet delivery by utilizing 4096 entry forwarding provides access to all PHY registers table with 256kByte frame buffer - In-band management via any of the data ports - Jumbo packet support up to 9000 bytes - I/O pin strapping facility to set certain register bits from - Port mirroring/monitoring/sniffing: I/O pins at reset time ingress and/or egress traffic to any port Power Management - Rapid spanning tree protocol (RSTP) support for topol- - IEEE 802.3az Energy Efficient Ethernet (EEE) ogy management and ring/linear recovery - Energy detect power-down mode on cable disconnect - Multiple spanning tree protocol (MSTP) support - Dynamic clock tree control One Configurable External MAC Port - Unused ports can be individually powered down - Reduced Gigabit Media Independent Interface - Full-chip software power-down (RGMII) v2.0 - Wake-on-LAN (WoL) standby power mode with PME - Reduced Media Independent Interface (RMII) v1.2 interrupt output for system wake upon triggered events with 50MHz reference clock input/output optionvm - Media Independent Interface (MII) in PHY/MAC mode 2017-2019 Microchip Technology Inc. DS00002327E-page 1KSZ8565R TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: