LAN9117 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Reduced Power Modes Highlights - Numerous power management modes Member of LAN9118 Family optimized for - Wake on LAN* medium-high performance applications - Magic packet wakeup* Easily interfaces to most 16-bit embedded CPUs - Wakeup indicator event signal Efficient architecture with low CPU overhead - Link Status Change Integrated PHY supports external PHY via MII Single chip Ethernet controller interface - Fully compliant with IEEE 802.3/802.3u stan- Supports audio & video streaming over Ethernet: dards 1-2 high-definition (HD) MPEG2 streams - Integrated Ethernet MAC and PHY - 10BASE-T and 100BASE-TX support Medium-high speed member of LAN9118 Family (all members are pin-compatible) - Full- and Half-duplex support - Full-duplex flow control - Backpressure for half-duplex flow control Target Applications - Preamble generation and removal Medium-range Cable, satellite, and IP set-top - Automatic 32-bit CRC generation and check- boxes ing Digital video recorders and DVD recorders/play- - Automatic payload padding and pad removal - Loop-back modes ers High definition televisions Flexible address filtering modes - One 48-bit perfect address Digital media clients/servers and home gateways - 64 hash-filtered multicast addresses Video-over IP Solutions, IP PBX & video phones - Pass all multicast Wireless routers & access points - Promiscuous mode High-end audio distribution systems - Inverse filtering - Pass all incoming with status report Key Benefits - Disable reception of broadcast packets Integrated Ethernet PHY Non-PCI Ethernet Controller for medium-high per- formance applications - Auto-negotiation - Automatic polarity detection and correction - 16-bit interface with fast bus cycle times - Burst-mode read support High-Performance host bus interface - External MII Interface - Simple, SRAM-like interface Eliminates dropped packets - 16-bit data bus - Large, 16Kbyte FIFO memory that can be - Internal buffer memory can store over 200 allocated to RX or TX functions packets - One configurable host interrupt - Supports automatic or host-triggered PAUSE Miscellaneous features and back-pressure flow control - Low profile 100-pin, TQFP RoHS Compliant Minimizes CPU overhead package - Supports Slave-DMA - Integral 1.8V regulator - Interrupt Pin with Programmable Hold-off - General Purpose Timer timer - Support for optional EEPROM Reduces system cost and increases design flexi- - Support for 3 status LEDs multiplexed with bility Programmable GPIO signals - SRAM-like interface easily interfaces to most 3.3V Power Supply with 5V tolerant I/O embedded CPUs or SoCs 0 to 70 C - Low-cost, low--pin count non-PCI interface * Third-party brands and names are the property of their for embedded designs respective owners. 2005-2016 Microchip Technology Inc. DS00002267A-page 1LAN9117 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: