KSZ8852HLEWA Microchip

KSZ8852HLE Two-Port 10/100 Ethernet Switch with 8-/16-Bit Host Interface IEEE 802.1p/Q Tag Insertion or Removal on a Features Per-Port Basis (Egress) and Support Management Capabilities: Double-Tagging The KSZ8852 includes all the Functions of a 10/ VLAN ID Tag/Untag Options on Per Port Basis 100BASE-T/TX Switch System which Combines a Fully Compliant With IEEE 802.3/802.3u Switch Engine, Frame Buffer Management, Standards Address Look-Up Table, Queue Management, IEEE 802.3x Full-Duplex with Force Mode Option MIB Counters, Media Access Controllers (MAC) and Half-Duplex Backpressure Collision Flow and PHY Transceivers Control Non-Blocking Store-and-Forward Switch Fabric IEEE 802.1w Rapid Spanning Tree Protocol Assures Fast Packet Delivery by Utilizing 1024 Support Entry Forwarding Table IGMP v1/v2/v3 Snooping for Multicast Packet Port Mirroring/Monitoring/Sniffing: Ingress and/or Filtering Egress Traffic to Any Port QoS/CoS Packets Prioritization Support: 802.1p, MIB Counters for Fully Compliant Statistics DiffServ-Based and Re-Mapping Of 802.1p Gathering-34 Counters Per Port Priority Field Per Port Basis on Four Priority Loopback Modes for Remote Failure Diagnostics Levels Rapid Spanning Tree Protocol Support (RSTP) for IPv4/IPv6 QoS Support Topology Management and Ring/Linear Recovery IPv6 Multicast Listener Discovery (MLD) Snooping Support Robust PHY Ports Programmable Rate Limiting at the Ingress and Two Integrated IEEE 802.3/802.3u Compliant Egress Ports Ethernet Transceivers Supporting 10BASE-T and Broadcast Storm Protection 100BASE-TX On-Chip Termination Resistors and Internal 1K Entry Forwarding Table with 32K Frame Buffer Biasing for Differential Pairs to Reduce Power Four Priority Queues with Dynamic Packet HP Auto MDI/MDI-X Crossover Support Mapping for IEEE 802.1P, IPv4 TOS (DIFFSERV), IPv6 Traffic Class, Etc. Eliminating the Need to Differentiate Between Straight or Crossover Cables in Applications Source Address Filtering for Implementing Ring Topologies MAC Ports Comprehensive Configuration Registers Access Three Internal Media Access Control (MAC) Units Complete Register Access Via the Parallel Host 2Kbyte Jumbo Packet Support Interface Tail Tagging Mode (One Byte Added Before FCS) Facility to Load MAC Address from EEPROM At Support at Port 3 to Inform the Processor which Power Up and Reset Time Ingress Port Receives the Packet and its Priority I/O Pin Strapping Facility to Set Certain Register Programmable MAC Addresses for Port 1 and Bits from I/O Pins at Reset Time Port 2 and Self-Address Filtering Support Control Registers Configurable On-The-Fly MAC Filtering Function to Filter or Forward Unknown Unicast Packets Host Interface Advanced Switch Capabilities Selectable 8-bit or 16-bit Wide Interface Non-Blocking Store-and-Forward Switch Fabric Supports Big- and Little-Endian Processors Assures Fast Packet Delivery By Utilizing 1024 Indirect Data Bus for Data, Address and Byte Entry Forwarding Table Enable to Access any I/O Registers and RX/TX IEEE 802.1Q VLAN for Up To 16 Groups with a FIFO Buffers Full Range of VLAN IDs Large Internal Memory with 12KByte for RX FIFO and 6Kbytes for TX FIFO Programmable Low, High and Overrun Water 2018 Microchip Technology Inc. DS00002761A-page 1KSZ8852HLE Marks for Flow Control in RX FIFO Applications Efficient Architecture Design with Configurable General and Industrial Ethernet Applications Host Interrupt Schemes to Minimize Host CPU Wireless LAN Access Point and Gateway Overhead and Utilization Set Top / Game Box Queue Management Unit (QMU) Supervises Data Test and Measurement Equipment Transfers Across this Interface Automotive Power and Power Management Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V Integrated Low-Voltage (~1.3V) Low-Noise Regulator (LDO) Output for Digital and Analog Core Power Supports IEEE P802.3az Energy Efficient Ethernet (EEE) To Reduce Power Consumption In Transceivers In LPI State Full-Chip Hardware or Software Power Down (All Registers Value are not Saved and Strap-In Value will Re-Strap after Releasing the Power Down) Energy Detect Power Down (EDPD), which Disables the PHY Transceiver when Cables are Removed Wake On LAN Supported with Configurable Packet Control Dynamic Clock Tree Control to Reduce Clocking in Areas not in Use Power Consumption Less than 0.5W Additional Features Single 25 MHz +50 ppm Reference Clock Requirement Comprehensive Programmable Two LED Indica- tors Support for Link, Activity, Full/Half Duplex and 10/100 Speed Packaging Commercial Temperature Range: 0C to +70C and Extended Industrial Temperature Ranges: 40C to +105C and 40C to +115C 64-pin (10 mm 10 mm) Lead Free (RoHS) LQFP Package with Heat Exposed Ground Paddle for Low Thermal Resistance 0.11 m Technology for Lower Power Consumption DS00002761A-page 2 2018 Microchip Technology Inc.