KSZ8873MML Integrated 3-Port 10/100 Managed Switch with PHY - Full-Duplex IEEE 802.3x Flow Control (PAUSE) Features with Force Mode Option Advanced Switch Features - Half-Duplex Back Pressure Flow Control - IEEE 802.1q VLAN Support for Up to 16 Groups - HP Auto MDI-X for Reliable Detection of and (Full Range of VLAN IDs) Correction for Straight-Through and Crossover - VLAN ID Tag/Untag Options, Per Port Basis Cables with Disable and Enable Option - IEEE 802.1p/q Tag Insertion or Removal on a - MAC MII Interface Supports both MAC Mode Per Port Basis (Egress) and PHY Mode - Programmable Rate Limiting at the Ingress and -LinkMD TDR-Based Cable Diagnostics Permit Egress on a Per Port Basis Identification of Faulty Copper Cabling - Broadcast Storm Protection with Percent Con- - Comprehensive LED Indicator Support for Link, trol (Global and Per Port Basis) Activity, Full-/Half-Duplex, and 10/100 Speed - IEEE 802.1d Rapid Spanning Tree Protocol - HBM ESD Rating 3 kV Support Switch Monitoring Features - Tail Tag Mode (1 byte Added before FCS) Sup- - Port Mirroring/Monitoring/Sniffing: Ingress and/ port at Port 3 to Inform the Processor which or Egress Traffic to Any Port or MII Ingress Port Receives the Packets - MIB Counters for Fully Compliant Statistics - Bypass Feature that Automatically Sustains the Gathering, 34 MIB Counters Per Port Switch Function between Port 1 and Port 2 - Loopback Modes for Remote Diagnostic of Fail- when CPU (Port 3 Interface) Goes into Sleep ure Mode Low Power Dissipation - Self-Address Filtering Support - Full-Chip Software Power-Down (Register Con- - Individual MAC Address for Port 1 and Port 2 figuration Not Saved) - IGMP Snooping (IPv4) Support for Multicast - Full-Chip Hardware Power-Down (Register Packet Filtering Configuration Not Saved) - IPv4/IPv6 QoS Support - Energy-Detect Mode Support - MAC Filtering Function to Forward Unknown - Dynamic Clock Tree Shutdown Feature Unicast Packets to Specified Port - Per Port Based Software Power-Save on PHY Comprehensive Configuration Register Access (Idle Link Detection, Register Configuration Pre- - Serial Management Interface (SMI) to All Inter- served) nal Registers - Voltages: Single 3.3V Supply with Internal 1.8V - MII Management (MIIM) Interface to PHY Reg- LDO for 3.3V VDDIO isters 2 - Optional 3.3V, 2.5V, and 1.8V for VDDIO - High Speed SPI and I C Interface to All Internal - Transceiver Power 3.3V for VDDA 3.3 Registers Industrial Temperature Range: 40C to +85C - I/O Pins Strapping and EEPROM to Program Available in a 64-Pin LQFP, Lead-Free Package Selective Registers in Unmanaged Switch Mode Applications - Control Registers Configurable on the Fly (Port- VoIP Phone Priority, 802.1p/d/q, AN) QoS/CoS Packet Prioritization Support Set-Top/Game Box Automotive Ethernet - Per Port, 802.1p and DiffServ-Based - Re-Mapping of 802.1p Priority Field Per Port Industrial Control Basis, Four Priority Levels IPTV POF Proven Integrated 3-Port 10/100 Ethernet Switch SOHO Residential Gateway - 3rd Generation Switch with Three MACs and Broadband Gateway/Firewall/VPN One PHY Fully Compliant with IEEE 802.3u Integrated DSL/Cable Modem Standard Wireless LAN Access Point + Gateway - Non-Blocking Switch Fabric Ensures Fast Standalone 10/100 Switch Packet Delivery by Utilizing a 1k MAC Address Lookup Table and a Store-and-Forward Archi- tecture 2018 Microchip Technology Inc. DS00002776A-page 1KSZ8873MML TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: