FIFO, Flow Control, VLAN Tagging, Priority KSZ8895MLU Integrated 5-Port 10/100 Managed Switch Revision 1.2 General Description The KSZ8895MLU is a highly-integrated Layer 2- The KSZ8895MLU consists of 10/100 PHYs with managed 5-port switch with an optimized design and patented and enhanced mixed-signal technology, media plentiful features, qualified to meet AEC-Q100 standard access control (MAC) units, a high-speed non-blocking for automotive applications. It is designed for cost- switch fabric, a dedicated address lookup engine, and an sensitive 10/100Mbps 5-port switch systems with on-chip on-chip frame buffer memory. The KSZ8895MLU termination, lowest power consumption and internal core contains five MACs and four integrated PHYs. All PHYs power controller. These features will save more system support 10/100Base-T/TX. cost. It has 1.4Gbps high-performance memory All registers of MACs and PHYs units can be managed bandwidth, shared memory based switch fabric with full by the SPI interface or the SMI interface. MIIM registers non-blocking configuration. It also provides an extensive of the PHYs can be accessed through the MDC/MDIO feature set such as power management, programmable interface. EEPROM can set all control registers for the rate limit and priority ratio, tag/port-based VLAN, packets unmanaged mode. filtering, quality-of-service (QoS) four-queue The KSZ8895MLU provides multiple CPU control/data prioritization, management interface, and MIB counters. interfaces to effectively address both current and Port 5 is a MAC 5 MII interface with PHY mode as emerging fast Ethernet applications. default at switch side. The SW5-MII interface can be Datasheets and support documentation are available on connected to a processor with a MAC MII interface. Micrels web site at: www.micrel.com. Functional Diagram KSZ8895MLU 10/100 10/100 T/Tx 1 1K Look Up Auto MDI/MDIX MAC 1 PHY1 Engine 10/100 10/100 T/Tx 2 Auto MDI/MDIX MAC 2 PHY2 Queue Mgmnt 10/100 10/100 Auto MDI/MDIX T/Tx 3 MAC 3 PHY3 Buf f er 10/100 10/100 Mgmnt Auto MDI/MDIX T/Tx 4 MAC 4 PHY4 10/100 SW5-MII Frame MAC 5 Buf fers MDC,MDI/O for MIIM and SMI SNI SNI MIB Control Reg SPI I/F SPI Counters LED0 5:1 LED1 5:1 Control EEPROM LED I/F LED2 5:1 I/F Registers Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KSZ8895MLU Features Advanced Switch Features IEEE 802.1q VLAN support for up to 128 VLAN groups Non-blocking switch fabric assures fast packet delivery by (full-range 4096 of VLAN IDs). utilizing a 1K MAC address lookup table and a store-and- forward architecture. Static MAC table supports up to 32 entries. On-chip 64Kbyte memory for frame buffering (not shared with VLAN ID tag/untag options, per port basis. 1K unicast address table). IEEE 802.1p/q tag insertion or removal on a per port Full duplex IEEE 802.3x flow control (PAUSE) with force mode basis based on ingress port (egress). option. Programmable rate limiting at the ingress and egress on Half-duplex back pressure flow control. a per port basis. HP Auto MDI/MDI-X and IEEE Auto crossover support. Jitter-free per packet based rate-limiting support. Port 5 MAC5 SW5-MII interface supports PHY mode and MAC Broadcast storm protection with percentage control mode. (global and per port basis). 7-wire serial network interface (SNI) support for legacy MAC. IEEE 802.1d rapid spanning tree protocol RSTP support. Per port LED Indicators for link, activity, and 10/100 speed. Tail tag mode (1byte added before FCS) support at Port Register port status support for link, activity, full/half duplex 5 to inform the processor which ingress port receives and 10/100 speed. the packet. On-chip terminations and internal biasing technology for cost 1.4Gbps high-performance memory bandwidth and down and lowest power consumption. shared memory-based switch fabric with fully non- Switch Monitoring Features blocking configuration. Port mirroring/monitoring/sniffing: ingress and/or egress traffic MII with MAC 5 on Port 5, SW5-MII for MAC 5 MII to any port or MII. interface. MIB counters for fully-compliant statistics gathering 34 MIB Enable/Disable option for huge frame size up to 2000 counters per port. bytes per frame. Loop-back support for MAC, PHY, and remote diagnostic of IGMP v1/v2 snooping (Ipv4) support for multicast packet failure. filtering. Interrupt for the link change on any ports. IPv4/IPv6 QoS support. Low Power Dissipation Support unknown unicast/multicast address and Full-chip hardware power-down. unknown VID packet filtering. Full-chip software power-down/per port software power down. Self-address filtering. Energy-detect mode support <100mW full-chip power Comprehensive Configuration Register Access consumption when all ports have no activity. Serial management interface (MDC/MDIO) to all PHYs Very-low, full-chip power consumption (<0.5W), without extra registers and SMI interface (MDC/MDIO) to all registers. power consumption on transformers. 2 High-speed SPI (up to 25MHz) and I C master Interface Dynamic clock-tree shutdown feature. to all internal registers. Voltages: Single 3.3V supply with 3.3V VDDIO and Internal I/0 pins strapping and EEPROM to program selective 1.2V LDO controller enabled or external 1.2V LDO solution: registers in unmanaged switch mode. Analog VDDAT 3.3V only Control registers configurable on the fly (port-priority, VDDIO support 3.3V, 2.5V, and 1.8V 802.1p/d/q, AN). Low 1.2V core power QoS/CoS Packet Prioritization Support 0.13um CMOS technology Per port, 802.1p and DiffServ-based. Industrial Temperature Range: 40 C to +85 C. 1/2/4-queue QoS prioritization selection. Available in 128-pin LQFP, lead-free package. Programmable weighted fair queuing for ratio control. Re-mapping of 802.1p priority field per port basis. Applications Integrated 5-Port 10/100 Ethernet Switch In-vehicle diagnostics (OBD) New generation switch with five MACs and five PHYs High-speed software download fully compliant with IEEE 802.3u standard. Gateway switch Non-blocking switch fabric assures fast packet delivery Head unit by utilizing a 1K MAC address lookup table and a store- Rear seat entertainment and-forward architecture. New generation switch with five MACs and five PHYs fully compliant with IEEE 802.3u standard. April 28, 2014 2 Revision 1.2