KSZ8895MQ/RQ/FMQ Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Revision 1.7 General Description The KSZ8895MQ/RQ/FMQ is a highly-integrated, The KSZ8895 family offers three configurations, Layer 2 managed, five-port switch with numerous providing the flexibility to meet different requirements: features designed to reduce system cost. Intended for KSZ8895MQ: Five 10/100Base-T/TX transceivers, cost-sensitive 10/100Mbps five-port switch systems one SW5-MII and one P5-MII interface, with low power consumption, on-chip termination, and KSZ8895RQ: Five 10/100Base-T/TX transceivers, internal core power controllers, it supports one SW5-RMII and one P5-RMII interface high-performance memory bandwidth and shared memory-based switch fabric with non-blocking KSZ8895FMQ: Three 10/100Base-T/TX transceivers on Ports 1, 2, 5 and two 100Base-FX configuration. Its extensive feature set includes power management, programmable rate limit and priority transceivers on Ports 3, 4, one SW5-MII and one P5-MII interface ratio, tag/port-based VLAN, packets filtering, four-queue QoS prioritization, management interfaces, and MIB counters. The KSZ8895 family provides All registers of MACs and PHYs units can be multiple CPU data interfaces to effectively address managed by the SPI or the SMI interface. MIIM both current and emerging fast Ethernet applications registers can be accessed through the MDC/MDIO when port 5 is configured to separate MAC5 with interface. EEPROM can set all control registers for the SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces. unmanaged mode. KSZ8895MQ/RQ/FMQ are 128-pin PQFP packages. Functional Diagram Note: SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5. Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 Micrel, Inc. KSZ8895MQ/RQ/FMQ Features On-chip 64Kbyte memory for frame buffering (not shared with Advanced Switch Features 1K unicast address table). IEEE 802.1q VLAN support for up to 128 active VLAN groups Full duplex IEEE 802.3x flow control (PAUSE) with force (full-range 4096 of VLAN IDs). mode option. Static MAC table supports up to 32 entries. Half-duplex back pressure flow control. VLAN ID tag/untag options, per port basis HP Auto MDI/MDI-X and IEEE Auto crossover support. IEEE 802.1p/q tag insertion or removal on a per port basis SW-MII interface supports both MAC mode and PHY mode. based on ingress port (egress). 7-wire serial network interface (SNI) support for legacy MAC. Programmable rate limiting at the ingress and egress on a per Per port LED Indicators for link, activity, and 10/100 speed. port basis. Register port status support for link, activity, full/half duplex Jitter-free per packet based rate limiting support. and 10/100 speed. Broadcast storm protection with percentage control (global On-chip terminations and internal biasing technology for cost and per port basis). down and lowest power consumption. IEEE 802.1d rapid spanning tree protocol RSTP support. Switch Monitoring Features Tail tag mode (1 byte added before FCS) support at Port 5 to Port mirroring/monitoring/sniffing: ingress and/or egress traffic inform the processor which ingress port receives the packet. to any port or MII. 1.4Gbps high-performance memory bandwidth and shared MIB counters for fully compliant statistics gathering 34 MIB memory-based switch fabric with fully counters per port. non-blocking configuration. Loop-back support for MAC, PHY and remote diagnostic of Dual MII with MAC5 and PHY5 on port 5, SW5-MII/RMII for failure. MAC 5 and P5-MII/RMII for PHY 5. Interrupt for the link change on any ports. Enable/Disable option for huge frame size up to 2000 Bytes per frame. Low Power Dissipation IGMP v1/v2 snooping (Ipv4) support for multicast packet Full-chip hardware power-down. filtering. Full-chip software power-down and per port software power IPv4/IPv6 QoS support. down. Support unknown unicast/multicast address and unknown VID Energy-detect mode support < 100mW full chip-power packet filtering. consumption when all ports have no activity. Self-address filtering. Very low full chip power consumption (<0.5W), without extra power consumption on transformers. Comprehensive Configuration Register Access Dynamic clock tree shutdown feature. Serial management interface (MDC/MDIO) to all PHYs registers and SMI interface (MDC/MDIO) to all registers. Voltages: Single 3.3V supply with 3.3V VDDIO and Internal 2 1.2V LDO controller enabled, or external 1.2V LDO solution. High speed SPI (up to 25MHz) and I C master Interface to all internal registers. Analog VDDAT 3.3V only. I/0 pins strapping and EEPROM to program selective VDDIO support 3.3V, 2.5V and 1.8V. registers in unmanaged switch mode. Low 1.2V core power . Control registers configurable on the fly (port-priority, 0.13m CMOS technology. 802.1p/d/q, AN). Commercial temperature range: 0C to +70C. QoS/CoS Packet Prioritization Support Industrial Temperature Range: -40C to +85C. Per port, 802.1p and DiffServ-based. Available in 128-pin PQFP lead-free package. 1/2/4-queue QoS prioritization selection. Applications Programmable weighted fair queuing for ratio control. VoIP phone Re-mapping of 802.1p priority field per port basis. Set-top/game box Integrated Five-Port 10/100 Ethernet Switch Automotive New generation switch with five MACs and five PHYs with Industrial control fully compliant with IEEE 802.3u standard. IPTV POF PHYs designed with patented enhanced mixed-signal technology. SOHO residential gateway Non-blocking switch fabric assures fast packet delivery by Broadband gateway/firewall/VPN utilizing a 1K MAC address lookup table and a store-and- Integrated DSL/cable modem forward architecture. Wireless LAN access point + gateway Standalone 10/100 switch Revision 1.7 March 19, 2014 2