FIFO, Flow Control, VLAN Tagging, Priority KS8995M Micrel, Inc. KS8995M Integrated 5-Port 10/100 Managed Switch Rev 1.13 General Description Features The KS8995M is a highly integrated Layer-2 managed switch Integrated switch with five MACs and five Fast Ethernet with optimized BOM (Bill of Materials) cost for low port count, transceivers fully compliant to IEEE 802.3u standard cost-sensitive 10/100Mbps switch systems. It also provides Shared memory based switch fabric with fully non- an extensive feature set such as tag/port-based VLAN, QoS blocking configuration (Quality of Service) priority, management, MIB counters, dual 1.4Gbps high-performance memory bandwidth MII interfaces and CPU control/data interfaces to effectively 10BaseT, 100BaseTX and 100BaseFX modes (FX in address both current and emerging Fast Ethernet applica- Ports 4 and 5) tions. Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII) The KS8995M contains five 10/100 transceivers with pat- IEEE 802.1q tag-based VLAN (16 VLANs, full-range ented mixed-signal low-power technology, five MAC (Media VID) for DMZ port, WAN/LAN separation or inter-VLAN Access Control) units, a high-speed non-blocking switch switch links fabric, a dedicated address look-up engine, and an on-chip VLAN ID tag/untag options, per-port basis frame buffer memory. Programmable rate limiting 0Mbps to 100Mbps, ingress All PHY units support 10BaseT and 100BaseTX. In addition, and egress port, rate options for high and low priority, two of the PHY units support 100BaseFX (Ports 4 and 5). per-port-basis All support documentation can be found on Micrels web site Flow control or drop packet rate limiting (ingress port) at: www.micrel.com. Integrated MIB counters for fully compliant statistics gathering, 34 MIB counters per port Functional Diagram 10/100 10/100 Auto 1K look-up MAC 1 MDI/MDIX T/Tx 1 Engine 10/100 Auto 10/100 MDI/MDIX MAC 2 T/Tx 2 Queue Mgmnt 10/100 10/100 Auto MDI/MDIX T/Tx 3 MAC 3 Buffer 10/100 10/100 Auto Mgmnt T/Tx/Fx 4 MAC 4 MDI/MDIX 10/100 10/100 Auto Frame T/Tx/Fx 5 MAC 5 MDI/MDIX Buffers MII-P5 MDC, MDI/O SNI MII-SW or SNI MIB Control Reg I/F SPI Counters LED0 5:1 LED1 5:1 Control EEPROM LED I/F LED2 5:1 Registers I/F KS8995M Micrel, Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 944-0970 KS8995M Micrel, Inc. Features (continued) Applications Enable/Disable option for huge frame size up to 1916 Broadband gateway/firewall/VPN bytes per frame Integrated DSL or cable modem multi-port router IGMP v1/v2 snooping for multicast packet filtering Wireless LAN access point plus gateway Special tagging mode to send CPU info on ingress Home networking expansion packets port value Standalone 10/100 switch SPI slave (complete) and MDIO (MII PHY only) serial Hotel/campus/MxU gateway management interface for control of register configura- Enterprise VoIP gateway/phone tion FTTx customer premise equipment MAC-id based security lock option Managed media converter Control registers configurable on-the-fly (port-priority, 802.1p/d/q, AN...) Ordering Information CPU read access to MAC forwarding table entries 802.1d Spanning Tree Protocol Part Number Temperature Range Package Port mirroring/monitoring/sniffing: ingress and/or egress KS8995M 0C to +70C 128-Pin PQFP traffic to any port or MII KSZ8995M 0C to +70C 128-Pin PQFP Lead Free Broadcast storm protection with percent control global KS8995MI 40C to +85C 128-Pin PQFP and per-port basis Optimization for fiber-to-copper media conversion Full-chip hardware power-down support (register configuration not saved) Per-port based software power-save on PHY (idle link detection, register configuration preserved) QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ based 802.1p/q tag insertion or removal on a per port basis (egress) MDC and MDI/O interface support to access the MII PHY control registers (not all control registers) MII local loopback support On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) Wire-speed reception and transmission Integrated look-up engine with dedicated 1K MAC addresses Full duplex IEEE 802.3x and half-duplex back pressure flow control Comprehensive LED support 7-wire SNI support for legacy MAC interface Automatic MDI/MDI-X crossover for plug-and-play Disable Automatic MDI/MDI-X option Low power: Core: 1.8V I/O: 2.5V or 3.3V 0.18m CMOS technology Commercial temperature range: 0C to +70C Industrial temperature range: 40C to +85C Available in 128-pin PQFP package M9999-070506 2 July 2006