LAN9352 2-Port 10/100 Managed Ethernet Switch with 8/16-Bit Non-PCI CPU Interface Ports Highlights - 2 internal 10/100 PHYs with HP Auto-MDIX High performance 2-port switch with VLAN, QoS support packet prioritization, rate limiting, IGMP monitoring - Fully compliant with IEEE 802.3 standards and management functions - 10BASE-T and 100BASE-TX support Interfaces to most 8/16-bit embedded controllers - 100BASE-FX support via external fiber transceiver - Full and half duplex support, full duplex flow control and 32-bit embedded controllers with an 8/16-bit - Backpressure (forced collision) half duplex flow control bus - Automatic flow control based on programmable levels Integrated Ethernet PHYs with HP Auto-MDIX - Automatic 32-bit CRC generation and checking Compliant with Energy Efficient Ethernet 802.3az - Programmable interframe gap, flow control pause value Wake on LAN (WoL) support - Auto-negotiation, polarity correction & MDI/MDI-X Integrated IEEE 1588v2 hardware time stamp unit 8/16-Bit Host Bus Interface Cable diagnostic support - Indexed register or multiplexed bus 1.8V to 3.3V variable voltage I/O - SPI / Quad SPI support Integrated 1.2V regulator for single 3.3V operation IEEE 1588v2 hardware time stamp unit - Global 64-bit tunable clock - Boundary clock: master / slave, one-step / two-step, Target Applications end-to-end / peer-to-peer delay Cable, satellite, and IP set-top boxes - Transparent Clock with Ordinary Clock: Digital televisions & video recorders master / slave, one-step / two-step, end-to-end / peer- VoIP/Video phone systems, home gateways to-peer delay - Fully programmable timestamp on TX or RX, Test/Measurement equipment, industrial automation timestamp on GPIO - 64-bit timer comparator event generation (GPIO or IRQ) Key Benefits Comprehensive power management features - 3 power-down levels Ethernet Switch Fabric - Wake on link status change (energy detect) - 32K buffer RAM, 512 entry forwarding table - Magic packet wakeup, Wake on LAN (WoL), wake on - Port based IEEE 802.1Q VLAN support (16 groups) broadcast, wake on perfect DA - Programmable IEEE 802.1Q tag insertion/removal - Wakeup indicator event signal - IEEE 802.1D spanning tree protocol support - 4 separate transmit queues available per port Power and I/O - Fixed or weighted egress priority servicing - Integrated power-on reset circuit - QoS/CoS Packet prioritization - Latch-up performance exceeds 150mA - Input priority determined by VLAN tag, DA lookup, TOS, per EIA/JESD78, Class II DIFFSERV or port default value - JEDEC Class 3A ESD performance - Programmable Traffic Class map based on input priority - Single 3.3V power supply on per port basis (integrated 1.2V regulator) - Remapping of 802.1Q priority field on per port basis - Programmable rate limiting at the ingress with coloring Additional Features and random early discard, per port / priority - Multifunction GPIOs - Programmable rate limiting at the egress with leaky - Ability to use low cost 25MHz crystal for reduced BOM bucket algorithm, per port / priority - IGMP v1/v2/v3 monitoring for Multicast packet filtering Packaging - Programmable broadcast storm protection with global % - Pb-free RoHS compliant 72-pin QFN or 80-pin TQFP- control and enable per port EP - Programmable buffer usage limits Available in commercial and industrial temp. ranges - Dynamic queues on internal memory - Programmable filter by MAC address Switch Management - Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any port or port pair - Fully compliant statistics (MIB) gathering counters 2015 Microchip Technology Inc. DS00001923A-page 1LAN9352 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: