LAN9353 3-Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII or Dual RMII Ports Highlights - Port 0: MII MAC, MII PHY, RMII PHY, RMII MAC modes High performance 3-port switch with VLAN, QoS - Port 1: Internal PHY, RMII MAC, RMII PHY modes packet prioritization, rate limiting, IGMP monitoring - Port 2: Internal PHY and management functions - 2 internal 10/100 PHYs with HP Auto-MDIX Interfaces at up to 200Mbps via Turbo MII support - 200Mbps Turbo MII (PHY or MAC mode) Integrated Ethernet PHYs with HP Auto-MDIX - Fully compliant with IEEE 802.3 standards Compliant with Energy Efficient Ethernet 802.3az - 10BASE-T and 100BASE-TX support Wake on LAN (WoL) support - 100BASE-FX support via external fiber transceiver Integrated IEEE 1588v2 hardware time stamp unit - Full and half duplex support, full duplex flow control Cable diagnostic support - Backpressure (forced collision) half duplex flow control 1.8V to 3.3V variable voltage I/O - Automatic flow control based on programmable levels Integrated 1.2V regulator for single 3.3V operation - Automatic 32-bit CRC generation and checking - Programmable interframe gap, flow control pause value - Auto-negotiation, polarity correction & MDI/MDI-X Target Applications IEEE 1588v2 hardware time stamp unit Cable, satellite, and IP set-top boxes - Global 64-bit tunable clock Digital televisions & video recorders - Boundary clock: master / slave, one-step / two-step, VoIP/Video phone systems, home gateways end-to-end / peer-to-peer delay - Transparent Clock with Ordinary Clock: Test/Measurement equipment, industrial automation master / slave, one-step / two-step, end-to-end / peer- to-peer delay Key Benefits - Fully programmable timestamp on TX or RX, timestamp on GPIO Ethernet Switch Fabric - 64-bit timer comparator event generation (GPIO or IRQ) - 32K buffer RAM, 512 entry forwarding table Comprehensive power management features - Port based IEEE 802.1Q VLAN support (16 groups) - 3 power-down levels - Programmable IEEE 802.1Q tag insertion/removal - IEEE 802.1D spanning tree protocol support - Wake on link status change (energy detect) - 4 separate transmit queues available per port - Magic packet wakeup, Wake on LAN (WoL), wake on - Fixed or weighted egress priority servicing broadcast, wake on perfect DA - QoS/CoS Packet prioritization - Wakeup indicator event signal - Input priority determined by VLAN tag, DA lookup, TOS, Power and I/O DIFFSERV or port default value - Integrated power-on reset circuit - Programmable Traffic Class map based on input priority - Latch-up performance exceeds 150mA on per port basis - Remapping of 802.1Q priority field on per port basis per EIA/JESD78, Class II - Programmable rate limiting at the ingress with coloring - JEDEC Class 3A ESD performance and random early discard, per port / priority - Single 3.3V power supply - Programmable rate limiting at the egress with leaky (integrated 1.2V regulator) bucket algorithm, per port / priority Additional Features - IGMP v1/v2/v3 monitoring for Multicast packet filtering - Programmable broadcast storm protection with global % - Multifunction GPIOs control and enable per port - Ability to use low cost 25MHz crystal for reduced BOM - Programmable buffer usage limits Packaging - Dynamic queues on internal memory - Pb-free RoHS compliant 64-pin QFN or 64-pin TQFP- - Programmable filter by MAC address EP Switch Management Available in commercial and industrial temp. ranges - Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any port or port pair - Fully compliant statistics (MIB) gathering counters 2015 Microchip Technology Inc. DS00001925A-page 1LAN9353 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors microchip.com. We welcome your feedback. Most Current Documentation To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at: