Short Form Data Sheet April 2012 MAX24288 IEEE 1588 Packet Timestamper and Clock and 1Gbps Parallel-to-Serial MII Converter General Description Highlighted Features Complete Hardware Support for IEEE 1588 The MAX24288 is a flexible, low-cost IEEE 1588 clock and timestamper with an SGMII or 1000BASE-X Ordinary, Boundary, and Transparent Clocks serial interface and a parallel MII interface that can Flexible Block for Any 1588 Architecture be configured for GMII, RGMII, or 10/100 MII. The 1588 Clock Hardware device provides all required hardware support for -8 Steerable by Software with 2 ns Time high-accuracy time and frequency synchronization -32 Resolution and 2 ns Period Resolution using the IEEE1588 Precision Time Protocol. In both 1ns Input Timestamp Accuracy and Output the transmit and receive directions 1588 packets are Edge Placement Accuracy identified and timestamped with high precision. System software makes use of these timestamps to Three Time/Frequency Controls: Direct Time Write, Time Adjustment, and High-Resolution determine the time offset between the system and its Frequency Adjustment timing master. Software can then correct any time error by steering the devices 1588 clock subsystem Programmable Clock and Time-Alignment I/O appropriately. The device provides the necessary I/O Input Event Timestamper Detects Incoming to time-synchronize with a 1588 master elsewhere in Time Alignment (e.g., 1 PPS) or Clock Edges the same system or to be the master to which slave Output Event Generator Provides Output Clock components can synchronize. Signal or Time Alignment Signal Built-In Support for Telecom Equipment Timing In addition, the MAX24288 is a full-featured, gigabit Architecture with Dual Redundant Timing Cards parallel-to-serial MII converter. It provides full SGMII 1588 Timestamping Hardware revision 1.8 compliance and also interfaces directly to 1588 v1 and v2 Packets, Transmit and Receive 1Gbps 1000BASE-X SFP optical modules. Packet Classifier Supports 1588 Over Ethernet, Applications IPv4/UDP, IPv6/UDP, or MPLS and Is Programmable for More Complex Stacks 1588-Enabled Equipment with 1G Ethernet Ports Supports 802.1Q VLAN Tags and MAC-in-MAC Wireless Base Stations and Controllers Switches, Routers, DSLAMs, PON Equipment One-Step Operation: On-the-Fly Timestamp Pseudowire Circuit Emulation Equipment Insertion or Transparent Clock Corrections No Test and Measurement Systems Need for Follow-Up Packets Industrial and Factory Automation Equipment Can Insert All Timestamps, Receive and Medical Equipment Transmit, Into Packets for Easy Software Access Optional Two-Step Operation Parallel-to-Serial MII Conversion Ordering Information Bidirectional Wire-Speed Interface Conversion PART TEMP RANGE PIN-PACKAGE Serial: 1000BASE-X or SGMII v1.8 (4, 6, or 8 Pin) MAX24288ETK+ 68 TQFN-EP* -40C to +85C Parallel: GMII, RGMII, or 10/100 MII +Denotes a lead(Pb)-free/RoHS-compliant package. Translates Link Speed and Duplex Mode *EP = Exposed pad. Negotiation Between MDIO and SGMII PCS SPI is a trademark of Motorola, Inc. Full Support for 1588 + Synchronous Ethernet MDIO and SPI Interfaces 1.2V Operation with 3.3V I/O 1 Short Form Data Sheet MAX24288 Application Examples Example 1: Single-Port 1588 Slave Node Local OSC 1.25G Serial Ethernet Processor SFP Module over fiber GMII 1588 -OR- -OR- MAX24288 Software MDIO Ethernet 1000BASE-T over copper PHY SGMII to frequency-syntonized or time-synchronized 1588 recovered clock, e.g. 25MHz system components 1588 recovered time, e.g. 1 PPS Example 2: Multiport System with Switch-Connected 1588 Slave Node 1.25G SFP Modules Serial SGMII Local or GbE Switch OSC Ethernet 1000BASE-T IC over fiber PHYs Processor GMII 1588 MAX24288 Software MDIO to other PHYs to frequency-syntonized or time-synchronized 1588 recovered clock, e.g. 25MHz system components 1588 recovered time, e.g. 1 PPS Example 3: Multiport System, Boundary or Transparent Clock, Port Card Logic 1.25G Serial Ethernet Processor SFP Module over fiber GMII 1588 -OR- -OR- MAX24288 Software MDIO Ethernet 1000BASE-T over copper PHY packet data to/from central switch function SGMII system clock, e.g. 25MHz from central system time, e.g. 1 PPS timing function line clock, e.g. 25MHz to central timing function for SyncE or line clocks from other ports 1588 + SyncE operation Example 4: Multiport System, Boundary or Transparent Clock, Central Timing Function Processor 1.25G GMII 1588 Serial MAX24288 Software packet data to/from central switch function MDIO 1588 Clock system time, e.g. 1 PPS Local OSC Stratum 3+ clk to all port cards system clock, e.g. 25MHz from port cards, line clocks, e.g. 25MHz DS31400 for SyncE or other clocks, Clock Sync IC 1588+SyncE operation various frequencies 2 MAC MAC MAC MAC